US4784969A
Expired / Lapsed
US
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Method of manufacturing a semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1987-04-28
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Granted: 1988-11-15
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Expires: 2007-04-28
Abstract
Abstract A method of manufacturing a semiconductor memory apparatus comprising a memory cell structure consisting of a transistor and capacitor. The method comprises the steps of forming a groove in the capacitor-forming region of a semiconductor substrate, forming a capacitor insulating film on the surface of the semiconductor substrate, including the inner surface of the groove, providing first and second contact holes in the capacitor insulating film, forming a first conductive film over the entire surface of thus produced structure, patterning the first conductive material, thereby providing a capacitor electrode covering the inner surface of the groove and first contact hole, and an interconnection electrode covering the second contact hole, forming a first interlayer insulating film over the surfaces of the capacitor electrode and interconnection electrode, forming a gate insulating film on that portion of the surface of the semiconductor substrate which lies between the capacitor electrode and interconnection electrode, forming a second conductive film over the entire surface of thus produced structure, and back-etching the second conductive film, to form a gate electrode on the gate insulating film which lies between the capacitor electrode and interconnection electrode.
Inventors
- 👤 Akihiro Nitayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:44
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/033; H10B12/30; H10B12/31; H10B12/318
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
181 words
A method of manufacturing a semiconductor memory device having a capacitor and transistor, which comprises the steps of: providing a groove in a capacitor-forming region of a semiconductor substrate; forming a capacitor-insulating film on the semiconductor substrate, including the inner surface of the groove; providing first and second holes in that portion of the capacitor-insulating film which is formed on the surface of the substrate; forming a first conductive film over the entire surface of thus produced structure; patterning said first conductive film, to form a capacitor electrode covering the inner surface of the groove and first contact hole, and an interconnection electrode covering the second contact hole; forming a first interlayer insulating film on the surfaces of the capacitor electrode and interconnection electrode; forming a gate insulating film on that portion of the substrate which lies between the capacitor electrode and interconnection electrode; forming a second conductive film over the entire surface of thus produced structure; and back-etching the second conductive film, to form a gate electrode on the gate-insulating film which lies between the capacitor electrode and interconnection electrode.
Claim 2
Independent Claim
181 words
A method of manufacturing a semiconductor memory device having a capacitor and transistor, which comprises the steps of: providing a groove in a capacitor-forming region of a semiconductor substrate; forming a capacitor-insulating film on the semiconductor substrate, including the inner surface of the groove; providing first and second holes in that portion of the capacitor-insulating film which is formed on the surface of the substrate; forming a first conductive film over the entire surface of thus produced structure; patterning said first conductive film, to form a capacitor electrode covering the inner surface of the groove and first contact hole, and an interconnection electrode covering the second contact hole; forming a first interlayer insulating film on the surfaces of the capacitor electrode and interconnection electrode; forming a gate insulating film on that portion of the substrate which lies between the capacitor electrode and interconnection electrode; forming a second conductive film over the entire surface of thus produced structure; and back-etching the second conductive film, to form a gate electrode on the gate-insulating film which lies between the capacitor electrode and interconnection electrode.
Claim 3
Dependent Claim
47 words
The method according to claim 1, wherein the first conductive film is prepared from impurity-doped polycrystalline silicon film; and the impurity is diffused from the capacitor electrode and interconnection electrode to the substrate, through the first and second contact holes, thereby to form source and drain regions.
Claim 4
Dependent Claim
43 words
The method according to claim 1, wherein the interlayer insulating film is removed after the formation of the gate electrode; and ion implantation is performed with the gate electrode, capacitor electrode, and interconnection electrode used as masks, thereby forming source and drain regions.
Claim 5
Dependent Claim
40 words
The method according to claim 1, wherein the interlayer insulating film is prepared by the thermal oxidation of the structure obtained up to this point, and ions are implanted into the substrate, through the insulation film formed on the substrate.
Claim 6
Dependent Claim
34 words
The method according to claim 4, wherein the gate insulation film is formed by a second thermal oxidation after the removal of the insulation film formed by said first thermal oxidation on the substrate.
Claim 7
Dependent Claim
17 words
The method according to claim 1, wherein the back-etching step is performed by use of anisotropic etching.
Claim 8
Dependent Claim
72 words
The method according to claim 1, wherein, after the formation of the gate electrode, a second interlayer insulating film is formed over the entire surface of the structure obtained up to this point; a third contact hole is provided in that portion of the second interlayer insulating film which is mounted on the interconnection electrode; and a bit line is formed in contact with the interconnection electrode, through the third contact hole.
Claim 9
Dependent Claim
18 words
The method according to claim 7, wherein the second and third contact holes do not overlap each other.
Claim 10
Independent Claim
199 words
A method of manufacturing a semiconductor memory device having a capacitor and transistor, which comprises the steps of: providing a groove in a capacitor-forming region of a semiconductor substrate; forming a capacitor-insulating film on the entire surface of the semiconductor substrate, including the inner surface of said groove; selectively etching that portion of said capacitor-insulating film which is formed on the surface of said substrate, to form first and second contact holes; depositing first conductive material on the insulating film having the contact holes to form a first conductive film; selectively etching said first conductive film, to form a capacitor electrode buried in the groove and first contact hole, and an interconnection electrode buried in the second contact hole; forming an interlayer insulating film on the surfaces of the capacitor electrode and interconnection electrode; forming a gate insulating film on that portion of the substrate which lies between the capacitor electrode and interconnection electrode; forming a second conductive film over the entire surface of thus produced structure; and back-etching the second conductive film, to leave as a gate electrode that portion of the second conductive film on the gate-insulating film which lies between the capacitor electrode and interconnection electrode.
Claim 11
Independent Claim
199 words
A method of manufacturing a semiconductor memory device having a capacitor and transistor, which comprises the steps of: providing a groove in a capacitor-forming region of a semiconductor substrate; forming a capacitor-insulating film on the entire surface of the semiconductor substrate, including the inner surface of said groove; selectively etching that portion of said capacitor-insulating film which is formed on the surface of said substrate, to form first and second contact holes; depositing first conductive material on the insulating film having the contact holes to form a first conductive film; selectively etching said first conductive film, to form a capacitor electrode buried in the groove and first contact hole, and an interconnection electrode buried in the second contact hole; forming an interlayer insulating film on the surfaces of the capacitor electrode and interconnection electrode; forming a gate insulating film on that portion of the substrate which lies between the capacitor electrode and interconnection electrode; forming a second conductive film over the entire surface of thus produced structure; and back-etching the second conductive film, to leave as a gate electrode that portion of the second conductive film on the gate-insulating film which lies between the capacitor electrode and interconnection electrode.
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JPS60175448A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-15 | 1992-05-16 | 1992-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-15 | 1996-05-16 | 1996-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-15 | 2000-05-16 | 2000-11-15 | $7700.00 | Window Closed / Lapsed |