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US5392129A
Expired / Lapsed
US
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Digital VCR signal processing apparatus for concealing uncorrectable errors
Assignee: Panasonic Holdings Corp
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Filing: 1993-06-25
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Granted: 1995-02-21
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Expires: 2013-06-25
Abstract
Abstract A signal processing apparatus for use in a digital video signal reproducing apparatus for reproducing digital signal presented in sync blocks is disclosed. Each sync block has a fixed area for low frequency data and five subsequent sync blocks define a sharing group for sharing high frequency data. The signal processing apparatus includes an inner and outer correction circuit for correcting errors in the sync blocks. An error flag is provided to a sync block which still has an error remaining after the processing in the correction circuit. A memory is provided for storing errorless sync blocks of one frame. A substitution switch is provided for passing the errorless sync blocks, but substituting a sync block stored in the memory for a sync block still having some errors. Five sync blocks produced from the substitution switch are held in a delay. When no substitute sync block is detected in the five sync blocks in the delay, the data in the five sync blocks are decoded by a bit rate reduction decoder. But, when one to four substitute sync block is detected in the five sync blocks in the delay, only the low frequency data of the five sync blocks in the fixed area are decoded by the bit rate reduction decoder.
Inventors
- 👤 Hideki Ohtaka
- 👤 Tatsuro Juri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:40
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; H04N5/94; H04N5/945; G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; H04N19/00; H04N19/85; H04N19/89; H04N19/895; H04N5/92; H04N5/926; H04N5/9261; H04N5/9264
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
204 words
A signal processing apparatus for use in a digital video signal reproducing apparatus for reproducing a digital signal presented in sync blocks each having a fixed area for storing low frequency data and an N (N is a positive integer) number of subsequent sync blocks defining a sharing group for sharing storing high frequency data, said signal processing apparatus comprising: error correction means for correcting errors in said sync blocks; error flag providing means for providing an error flag to a sync block which still has an error remaining after the processing in said error correction means and for selecting an errorless sync block which has no error; memory means for storing errorless sync blocks of at least one frame; substitution means for substituting a sync block stored in said memory means for a sync block having an error flag; substitution detection means for detecting a presence of at least one to (N-1) substitute sync block in said N sync blocks; and high frequency area trimming means for passing without any change said N sync blocks when no substitute sync block is detected, but for trimming the high frequency data when one to (N-1) substitute sync block is detected by said substitution detection means.
Claim 2
Dependent Claim
204 words
A signal processing apparatus for use in a digital video signal reproducing apparatus for reproducing a digital signal presented in sync blocks each having a fixed area for storing low frequency data and an N (N is a positive integer) number of subsequent sync blocks defining a sharing group for sharing storing high frequency data, said signal processing apparatus comprising: error correction means for correcting errors in said sync blocks; error flag providing means for providing an error flag to a sync block which still has an error remaining after the processing in said error correction means and for selecting an errorless sync block which has no error; memory means for storing errorless sync blocks of at least one frame; substitution means for substituting a sync block stored in said memory means for a sync block having an error flag; substitution detection means for detecting a presence of at least one to (N-1) substitute sync block in said N sync blocks; and high frequency area trimming means for passing without any change said N sync blocks when no substitute sync block is detected, but for trimming the high frequency data when one to (N-1) substitute sync block is detected by said substitution detection means.
Claim 3
Dependent Claim
50 words
A signal processing apparatus as claimed in claim 1, wherein said error correction means comprises an inner correction means for correcting said errors in said sync blocks using an inner correction parity and an outer correction means for correcting said errors in said sync blocks using an outer correction parity.
Claim 4
Dependent Claim
14 words
A signal processing apparatus as claimed in claim 1, wherein said N is five.
Claim 5
Dependent Claim
16 words
A signal processing apparatus as claimed in claim 1, further comprising a bit rate reduction decoder.
Claim 6
Dependent Claim
29 words
A signal processing apparatus as claimed in claim 1, further comprising a bit rate reduction decoding means for decoding sync blocks produced from said high frequency area trimming means.
Claim 7
Dependent Claim
20 words
A signal processing apparatus as claimed in claim 5, wherein said bit rate reduction decoding means employs an orthogonal transform.
Claim 8
Dependent Claim
251 words
A signal processing apparatus for use in a digital video signal reproducing apparatus for reproducing a digital signal presented in sync blocks each having a low frequency area and a high frequency area and an N (N is a positive integer) number of subsequent sync blocks defining a sharing group for sharing high frequency areas for storing high frequency data, said signal processing apparatus comprising: error correction means for correcting errors in said sync blocks; error flag providing means for providing an error flag to a sync block which still has an error remaining after the processing in said error correction means and for selecting an errorless sync block which has no error; memory means for storing errorless sync blocks of one frame; substitution means for passing said errorless sync block and for substituting a sync block stored in said memory means for a sync block having an error flag; holding means for holding said N number of sync blocks produced from said substitution means; substitution detection means for detecting a presence of at least one to (N-1) substitute sync block in said N sync blocks stored in said holding means; and high frequency area trimming means for passing without any change said N sync blocks produced from said holding means when no substitute sync block is detected, but for trimming the high frequency area from each of said N sync blocks produced from said holding means when one to (N-1) substitute sync block is detected by said substitution detection means.
Claim 9
Dependent Claim
251 words
A signal processing apparatus for use in a digital video signal reproducing apparatus for reproducing a digital signal presented in sync blocks each having a low frequency area and a high frequency area and an N (N is a positive integer) number of subsequent sync blocks defining a sharing group for sharing high frequency areas for storing high frequency data, said signal processing apparatus comprising: error correction means for correcting errors in said sync blocks; error flag providing means for providing an error flag to a sync block which still has an error remaining after the processing in said error correction means and for selecting an errorless sync block which has no error; memory means for storing errorless sync blocks of one frame; substitution means for passing said errorless sync block and for substituting a sync block stored in said memory means for a sync block having an error flag; holding means for holding said N number of sync blocks produced from said substitution means; substitution detection means for detecting a presence of at least one to (N-1) substitute sync block in said N sync blocks stored in said holding means; and high frequency area trimming means for passing without any change said N sync blocks produced from said holding means when no substitute sync block is detected, but for trimming the high frequency area from each of said N sync blocks produced from said holding means when one to (N-1) substitute sync block is detected by said substitution detection means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-20 | 1998-08-22 | 1999-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-20 | 2002-08-22 | 2003-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-20 | 2006-08-22 | 2007-02-21 | $7700.00 | Window Closed / Lapsed |