EP0203773A2 — Apparatus for decoding error correcting code

Claim 1

Independent Claim 139 words

Apparatus for decoding error detecting/correcting encoded digital information data that is reproduced from a record medium by a playback unit selectively operable at a normal speed mode and a varied-speed mode, in which said encoded data is derived by a product code formed of an inner code and an outer code; inner code decoder means receiving the reproduced signal for producing decoded digital information data and error-flag data-,--- n memory means including a buffer memory for storing said digital information data and a flag memory for storing said error flag data; outer code decoder means receiving said digital information data and said error flag data from said memory means for decoding said outer code; and error concealment means receiving the outer decoded data and concealing remaining uncorrected errors by interpolation, whereby error corrected, reproduced digital information data is produced.

Claim 2

Dependent Claim 139 words

Apparatus for decoding error detecting/correcting encoded digital information data that is reproduced from a record medium by a playback unit selectively operable at a normal speed mode and a varied-speed mode, in which said encoded data is derived by a product code formed of an inner code and an outer code; inner code decoder means receiving the reproduced signal for producing decoded digital information data and error-flag data-,--- n memory means including a buffer memory for storing said digital information data and a flag memory for storing said error flag data; outer code decoder means receiving said digital information data and said error flag data from said memory means for decoding said outer code; and error concealment means receiving the outer decoded data and concealing remaining uncorrected errors by interpolation, whereby error corrected, reproduced digital information data is produced.

Claim 3

Dependent Claim 77 words

Apparatus according to claim 1, in which said buffer memory comprises a plurality of individual memory units having respective address generating circuits and a serial-to-parallel-to-serial converter receiving said digital information data in serial form and converting it into parallel form for feeding to said plurality of memory units, and controller means connected to said serial-to-parallel-to-serial converter for controlling writing in and reading out of said plurality of memories, whereby said digital informatiqn data is rearranged in sequence.

Claim 4

Dependent Claim 207 words

Apparatus for decoding error detecting/correcting code that is derived from digital information data and redundant data used for detecting/correcting the information data, in which the digital information data and redundant data are reproduced by a playback unit at selectably normal and variabie speeds from a record medium, comprising: first decoding means for decoding said error detecting/correcting code and generating therefrom flag data indicating errors in said digital information data in association with said digital information data having no errors; first memory means connected for storing said digital information data derived from said first decoding means; second memory means connected for storing said flag data; and control means connected to receive a mode signal indicative of a selected speed of the playback unit for producing control signals fed to said first and second memory means, said control signals being operative when said mode signal indicates the normal playback speed to control said first and second memory means to have written therein said digital information and said flag data, respectively and said control signals being operative when said mode signal indicates a variable playback speed to control said first and second memory means to have written therein said digital information data having no errors and said flag data, respectively.

Claim 5

Dependent Claim 207 words

Apparatus for decoding error detecting/correcting code that is derived from digital information data and redundant data used for detecting/correcting the information data, in which the digital information data and redundant data are reproduced by a playback unit at selectably normal and variabie speeds from a record medium, comprising: first decoding means for decoding said error detecting/correcting code and generating therefrom flag data indicating errors in said digital information data in association with said digital information data having no errors; first memory means connected for storing said digital information data derived from said first decoding means; second memory means connected for storing said flag data; and control means connected to receive a mode signal indicative of a selected speed of the playback unit for producing control signals fed to said first and second memory means, said control signals being operative when said mode signal indicates the normal playback speed to control said first and second memory means to have written therein said digital information and said flag data, respectively and said control signals being operative when said mode signal indicates a variable playback speed to control said first and second memory means to have written therein said digital information data having no errors and said flag data, respectively.

Claim 6

Dependent Claim 196 words

An apparatus according to claim 3, wherein said error detecting/correcting code constructed from said digital information data is arranged in a matrix form, with first redundant data forming a first error detecting/correcting code for detecting or correcting error of a first series of said digital information data in a first direction of said matrix, and second redundant data forming a second error detecting/correcting code for detecting or correcting error of a second series of said digital information data in a second direction of said matrix, the digital information data, first redundant data and second redundant data being reproduced from said record medium by the playback apparatus, in which said first decoding means decodes said second error detecting or correcting code, and said first memory means stores said digital information data and first redundant data subjected to the decoding in said first decoding means for outputting said digital information data and first redundant data arranged in said first series of said first error detecting or correcting code; and further comprising second decoding means provided with said digital information data and first redundant data from said first memory means for decoding said first error detecting or correcting code.

Claim 7

Dependent Claim 185 words

Apparatus for decoding an error detecting and correcting code produced from digital information data reproduced from a record medium by a playback apparatus selectively operable in normal and varied playback speed modes, in which the code is a product code formed of an inner code and an outer code, comprising: an inner decoder for decoding the error detecting and correcting code and producing decoded digital information data and error flag data indicating error conditions of the digital information data; a memory means connected to have written therein said decoded digital information data and said error flag data; memory control means operably connected to said memory means for controlling writing and reading of said decoded digital information data and said error flag data into and out of said memory means in response to a selected playback speed mode; and an outer decoder connected to said memory means for decoding the digital information data and the error flag data from said memory means for producing an error corrected digital information signal, in which all errors of an extent determined by said inner and outer codes are corrected.

Claim 8

Dependent Claim 185 words

Apparatus for decoding an error detecting and correcting code produced from digital information data reproduced from a record medium by a playback apparatus selectively operable in normal and varied playback speed modes, in which the code is a product code formed of an inner code and an outer code, comprising: an inner decoder for decoding the error detecting and correcting code and producing decoded digital information data and error flag data indicating error conditions of the digital information data; a memory means connected to have written therein said decoded digital information data and said error flag data; memory control means operably connected to said memory means for controlling writing and reading of said decoded digital information data and said error flag data into and out of said memory means in response to a selected playback speed mode; and an outer decoder connected to said memory means for decoding the digital information data and the error flag data from said memory means for producing an error corrected digital information signal, in which all errors of an extent determined by said inner and outer codes are corrected.

Claim 9

Dependent Claim 35 words

Apparatus according to claim 5, further comprising error concealment means connected to said outer decoder for concealing errors in said error corrected digital information signal greater than said extent determined by inner and outer codes.

Claim 10

Dependent Claim 29 words

Apparatus according to claim 6, in which said error concealment means comprises interpolation means for concealing errors by interpolating a correct value of data based on adjacent correct data.

Claim 11

Dependent Claim 65 words

Apparatus according to claim 5, in which said memory means comprises a buffer memory and an error flag memory and said memory control means operates in response to an indication of the normal playback speed to control said buffer memory to have written therein only correct decoded digital information data and to control said error flag memory to have said error flag data written therein.

Claim 12

Dependent Claim 64 words

Apparatus according to claim 5 in which said memory means comprises a plurality of memory chips connected as a plurality of parallel channels for storing data from a serial-to-parallel-to-serial converter receiving a serial decode digital information signal from said first encoder, each of said memory chips being controlled to read/write data from said serial-to-parallel-to-serial converter by a control signal from said memory control means.

Claim 13

Dependent Claim 111 words

Apparatus according to claim 5, in which said memory means comprises a buffer memory and first and second error flag memories and said memory control means operates in response to an indication of a varied playback speed mode corresponding to a slow-motion playback for controlling said first error flag memory for storing error flag data indicating data already read and for controlling said second error flag means for storing error flag data from said first error flag data from said first error flag memory, whereby during the slow-motion mode data in said buffer memory is repeatedly read out and error flag data in said second error flag memory is read out.

Apparatus for decoding error correcting code

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag