EP0517141A2
Expired / Lapsed
EP
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High efficiency coding signal processing apparatus with error propagation influence reduction
Assignee: Toshiba Corp
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Filing: 1992-06-01
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Granted: —
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Expires: 2012-06-01
Abstract
Abstract According to a high efficiency coding signal processing apparatus of the present invention, in order to suppress error propagation, effectively correct errors, and reduce a signal deterioration upon repetitive coding processing, a bit rate reduction circuit (53) quantizes a video signal and outputs the resultant signal to low- and high-frequency encoders (71, 72, 75, 76). A first transmission sequence packet circuit (77) outputs low-frequency components at a predetermined period. A second transmission sequence packet circuit (79) sequences and outputs high-frequency components. Since the low-frequency components and the high-frequency components are separately sequenced and transmitted, the low-frequency components are free from the influence of errors caused in the high-frequency components.
Inventors
- 👤 Kenji C/O Intellectual Property Div. Shimoda
- 👤 Hitoshi c/o Intellectual Property Div. Takeda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 17:20
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/92; H04N5/926; H04N5/9261; H04N5/9264; H04N19/00; H04N19/10; H04N19/102; H04N19/115; H04N19/124; H04N19/134; H04N19/136; H04N19/14; H04N19/146; H04N19/149; H04N19/15; H04N19/157; H04N19/159; H04N19/169; H04N19/17; H04N19/172; H04N19/176; H04N19/18; H04N19/186; H04N19/30; H04N19/37; H04N19/46; H04N19/60; H04N19/85; H04N19/89; H04N21/00; H04N21/20; H04N21/23; H04N21/236; H04N21/40; H04N21/43; H04N21/434; H04N7/00; H04N7/24; H04N9/00; H04N9/79; H04N9/80; H04N9/804; H04N9/8042; H04N9/8047; H04N9/806; H04N9/8063; H04N9/8066; H04N9/87; H04N9/88; H04N9/888; H04N19/13; H04N19/65; H04N19/90; H04N19/91; H04N5/78; H04N5/782; H04N5/783
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
122 words
A high efficiency coding signal processing apparatus characterized by comprising: data compressing means (53) for performing frequency transformation of data in units of predetermined blocks within one frame and outputting transform coefficients for data compression; low-frequency component coding means (71, 76) for encoding low-frequency components of the transform coefficients from said data compressing means (53); high-frequency component coding means (72, 75) for encoding high-frequency components of the transform coefficients from said data compressing means (53); first transmission sequence packet means (72) for outputting data from said low-frequency component means (71, 76) at a predetermined period; and second transmission sequence packet means (79) for performing predetermined sequencing with respect to data from said high-frequency component coding means (72, 75) and outputting the data.
Claim 2
Dependent Claim
84 words
A high efficiency coding signal processing apparatus characterized by comprising: a variable-length data decoder (94) for decoding input variable-length data; a decoding error detector (161) for detecting data which cannot be decoded by said variable-length data decoder (94), and for determining validity of each decoded output; and replacing means (163) for replacing each decoded output from said variable-length data decoder (94) with a predetermined value at a timing based on the determination result from said decoding error detector (161), and outputting the resultant data.
Claim 3
Dependent Claim
119 words
A high efficiency coding signal processing apparatus characterized by comprising: decoding means (91) decoding input data encoded in units of predetermined blocks within one frame; a decoding error detector (161) for detecting data which cannot be decoded by said decoding means (91), and for determining validity of each decoded output; holding means (94) for holding each output from said decoding means; and data length estimation means (165) for receiving data of a block adjacent to an error block from said holding means (94), estimating a data length of the error block, and designating decoding start of data of a next block to said decoding means at a timing based on the determination result from said decoding error detector (161).
Claim 4
Dependent Claim
111 words
A high efficiency coding signal processing apparatus characterized by comprising: decoding means for decoding input data encoded in units of predetermined blocks within one frame; error detection means (91) for detecting an error in the input data; holding means (173) for holding each output from said decoding means; interpolation signal generating means (172) for determining correlation between data of an error block designated by said error detection means (91) and data of a block adjacent to the error block which is supplied from said holding means, thereby generating interpolation data; and replacing means (163) for replacing the data of the error block with the interpolation data, and outputting the resultant data.
References Cited (Backward Citations)
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