US5391892A — Semiconductor wafers having test circuitry for in…

Claim 1

Independent Claim 158 words

A semiconductor wafer comprising: a plurality of individual dies containing integrated circuits which are substantially isolated from each other; areas of distinct scribe line area which are separate from the individual dies, the wafer being severable along the scribe lines to physically singulate the dies; test cycling circuitry for test cycling the individual dies; a passivation layer; Vcc and Vss pads associated with the individual dies; electrical contacts extending through the passivation layer to the Vcc and Vss pads; a Vcc bus provided atop the passivation layer and atop the dies which electrically connects with a plurality of the Vcc pads and the test cycling circuitry; a Vss bus provided atop the passivation layer and atop the dies which electrically connects with a plurality of the Vss pads; and the Vcc And Vss busses each including respective straight-line portions extending fully between individual die circuitry areas, each straight-line portion overlying a plurality of the individual die circuitry areas.

Claim 2

Dependent Claim 158 words

A semiconductor wafer comprising: a plurality of individual dies containing integrated circuits which are substantially isolated from each other; areas of distinct scribe line area which are separate from the individual dies, the wafer being severable along the scribe lines to physically singulate the dies; test cycling circuitry for test cycling the individual dies; a passivation layer; Vcc and Vss pads associated with the individual dies; electrical contacts extending through the passivation layer to the Vcc and Vss pads; a Vcc bus provided atop the passivation layer and atop the dies which electrically connects with a plurality of the Vcc pads and the test cycling circuitry; a Vss bus provided atop the passivation layer and atop the dies which electrically connects with a plurality of the Vss pads; and the Vcc And Vss busses each including respective straight-line portions extending fully between individual die circuitry areas, each straight-line portion overlying a plurality of the individual die circuitry areas.

Claim 3

Dependent Claim 20 words

The semiconductor wafer of claim 1 wherein the test cycling circuitry comprises individual test cycling circuitry associated with individual dies.

Claim 4

Dependent Claim 18 words

The semiconductor wafer of claim 2 wherein the individual test cycling circuitry is provided on the individual dies.

Claim 5

Dependent Claim 54 words

The semiconductor wafer of claim 1 wherein the dies comprise memory array, and wherein the test cycling circuitry comprises: an address counter to sequentially address the memory array; a data generator to write data to the memory array; and control signal logic to control data access from the data generator to the memory array.

Claim 6

Dependent Claim 132 words

The semiconductor wafer of claim 1 wherein the dies comprise memory array, and wherein the test cycling circuitry comprises: an address counter to sequentially address the memory array; a data generator to write test data to the memory array; control signal logic to control data access from the data generator to the memory array; a comparison circuit coupled to receive the test data written from the data generator and to read actual data from the memory array, the comparison circuit comparing the test data written to the memory array with the actual data read from the memory array and producing an error detection signal when the test data is not the same as the actual data; and timing means for indicating when the error detection signal was produced by the comparison circuit.

Claim 7

Dependent Claim 62 words

The semiconductor wafer of claim 1 wherein the wafer comprises permanent Vcc and permanent Vss pads on the individual dies, and sacrificial Vcc and Vss pads associated with the dies, the respective permanent and sacrificial pads being connected relative to one another in parallel, the Vcc bus connecting with the sacrificial Vcc pads, the Vss bus connecting with the sacrificial Vss pads.

Claim 8

Dependent Claim 19 words

The semiconductor wafer of claim 6 wherein the sacrificial Vcc and Vss pads are provided on the individual dies.

Claim 9

Dependent Claim 103 words

The semiconductor wafer of claim 1 wherein the test cycling circuitry comprises individual test cycling circuitry formed on the individual dies, a cycling test pad being associated with the individual test cycling circuitry and being provided on the individual dies; the wafer further comprising: permanent Vcc and permanent Vss pads on the individual dies, and sacrificial Vcc and Vss pads on the individual dies, the respective permanent and sacrificial pads being connected relative to one another in parallel on the individual dies, the Vcc bus connecting with the individual die sacrificial Vcc pads, the Vss bus connecting with the individual sacrificial Vss pads.

Claim 10

Dependent Claim 17 words

The semiconductor wafer of claim 1 further comprising fuses between the Vcc bus and individual Vcc pads.

Claim 11

Dependent Claim 75 words

The semiconductor wafer of claim 1 wherein the wafer comprises permanent Vcc and permanent Vss pads on the individual dies, and sacrificial Vcc and Vss pads associated with the dies, the respective permanent and sacrificial pads being connected relative to one another in parallel, the Vcc bus connecting with the sacrificial Vcc pads, the Vss bus connecting with the sacrificial Vss pads, and fuses being provided between the Vcc bus and the sacrificial Vcc pads.

Claim 12

Dependent Claim 123 words

The semiconductor wafer of claim 1 wherein the test cycling circuitry comprises individual test cycling circuitry formed on the individual dies, a cycling test pad being associated with the individual test cycling circuitry and being provided on the individual dies and being engaged by the Vcc bus; the wafer further comprising: permanent Vcc and permanent Vss pads on the individual dies, and sacrificial Vcc and Vss pads on the individual dies, the respective permanent and sacrificial pads being connected relative to one another in parallel on the individual dies, the Vcc bus connecting with the individual die sacrificial Vcc pads, the Vss bus connecting with the individual sacrificial Vss pads, and fuses being provided between the Vcc bus and the sacrificial Vcc pads.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1998-02-20	1998-08-22	1999-02-21	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2002-02-20	2002-08-22	2003-02-21	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2006-02-20	2006-08-22	2007-02-21	$7700.00	Window Closed / Lapsed

Semiconductor wafers having test circuitry for individual dies

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag