Apparatus and method of encoding control data in a computer graphics system

Claim 1

A method of displaying images on a computer graphics system by encoding and decoding plural bit control data input to a decode logic circuit included therein, comprising the steps of: converting, by said decode logic circuit, a first bit from the plural bit control data into a class bit for defining plural subsets of said plural bit control data; designating a second bit of said plural bit control data as a control bit field to control a reset operation, the validity of said control bit field being dependent upon said class bit; controlling a window identification operation by outputting a first class of values, corresponding to one of the plural subsets, wherein said class bit indicates that said second bit is valid and a reset operation may be implemented; and controlling said window identification operation by outputting a second class of values, corresponding to another one of the plural subsets, wherein said class bit indicates that said second bit is invalid and a reset operation may not be implemented.

Claim 2

A method of displaying images on a computer graphics system by encoding and decoding plural bit control data input to a decode logic circuit included therein, comprising the steps of: converting, by said decode logic circuit, a first bit from the plural bit control data into a class bit for defining plural subsets of said plural bit control data; designating a second bit of said plural bit control data as a control bit field to control a reset operation, the validity of said control bit field being dependent upon said class bit; controlling a window identification operation by outputting a first class of values, corresponding to one of the plural subsets, wherein said class bit indicates that said second bit is valid and a reset operation may be implemented; and controlling said window identification operation by outputting a second class of values, corresponding to another one of the plural subsets, wherein said class bit indicates that said second bit is invalid and a reset operation may not be implemented.

Claim 4

A method of displaying images on a computer graphics system by encoding and decoding plural bit control data, input to a decode logic circuit, comprising the steps of: controlling a class designation operation to indicate whether simultaneous reset of attribute data is provided for pixels in an attribute buffer in said computer graphics system by converting a first bit of said plural bit control data; outputting a first subset of the plural bit control data from said decode logic circuit to control a window identification operation, said first subset being of a first class including said first bit and being dependent upon a value thereof to indicate that simultaneous reset of the attribute data is provided, said first subset being configured as an ordered n-tuple; outputting a second subset of the plural bit control data from said decode logic circuit to control said window identification operation, said second subset being of a second class including said first bit and being dependent upon the value thereof to indicate that simultaneous reset of the attribute data is not provided, said second subset being configured as an ordered n-tuple; designating, as one control value for controlling a reset operation, a second bit of the plural bit control data of the subset which has a predetermined position in the ordered n-tuple; and setting one binary value at a position other than said predetermined position in the ordered n-tuple of the subset and outputting a signal from said decode logic circuit to indicate reset of the attribute data in the attribute buffer only when said first bit is of a predetermined value.

Claim 5

A method of displaying images on a computer graphics system by encoding and decoding plural bit control data, input to a decode logic circuit, comprising the steps of: controlling a class designation operation to indicate whether simultaneous reset of attribute data is provided for pixels in an attribute buffer in said computer graphics system by converting a first bit of said plural bit control data; outputting a first subset of the plural bit control data from said decode logic circuit to control a window identification operation, said first subset being of a first class including said first bit and being dependent upon a value thereof to indicate that simultaneous reset of the attribute data is provided, said first subset being configured as an ordered n-tuple; outputting a second subset of the plural bit control data from said decode logic circuit to control said window identification operation, said second subset being of a second class including said first bit and being dependent upon the value thereof to indicate that simultaneous reset of the attribute data is not provided, said second subset being configured as an ordered n-tuple; designating, as one control value for controlling a reset operation, a second bit of the plural bit control data of the subset which has a predetermined position in the ordered n-tuple; and setting one binary value at a position other than said predetermined position in the ordered n-tuple of the subset and outputting a signal from said decode logic circuit to indicate reset of the attribute data in the attribute buffer only when said first bit is of a predetermined value.

Claim 13

An apparatus, included within a computer graphics system, for encoding and decoding plural bit control data input to a decode logic circuit included within said computer graphics system, comprising: means for converting, by said decode logic circuit a first bit from the plural bit control data into a class bit for defining plural subsets of said plural bit control data; means for designating a second bit of said plural bit control data as a control bit field to control a reset operation, the validity of said control bit field being dependent upon said class bit; means for controlling a window identification operation by outputting, from said decode logic circuit, a first class of control values corresponding to one of the plural subsets, wherein said class bit indicates that said second bit is valid and a reset operation may be implemented; and means for controlling said window identification operation by outputting a second class of values, corresponding to another one of the plural subsets, wherein said class bit indicates that said second bit is invalid and a reset operation may not be implemented.

Claim 14

An apparatus, included within a computer graphics system, for encoding and decoding plural bit control data input to a decode logic circuit included within said computer graphics system, comprising: means for converting, by said decode logic circuit a first bit from the plural bit control data into a class bit for defining plural subsets of said plural bit control data; means for designating a second bit of said plural bit control data as a control bit field to control a reset operation, the validity of said control bit field being dependent upon said class bit; means for controlling a window identification operation by outputting, from said decode logic circuit, a first class of control values corresponding to one of the plural subsets, wherein said class bit indicates that said second bit is valid and a reset operation may be implemented; and means for controlling said window identification operation by outputting a second class of values, corresponding to another one of the plural subsets, wherein said class bit indicates that said second bit is invalid and a reset operation may not be implemented.

Claim 16

An apparatus, included within a computer graphics system, for encoding and decoding plural bit control data, input to a decode logic circuit, comprising: means for controlling a class designation operation to indicate whether simultaneous reset of attribute data is provided for pixels in an attribute buffer in said computer graphics system by converting a first bit of said plural bit control data means for outputting a first subset of the plural bit control data from said decode logic circuit to control a window identification operation, said first subset being of a first class including said first bit for and being dependent upon a value thereof to indicate that simultaneous reset of the attribute data is provided, said first subset being configured as an ordered n-tuple; means for outputting a second subset of the plural bit control data from said decode logic circuit to control said windows identification operation, said second subset being of a second class including said first bit and being dependent upon the value thereof to indicate that simultaneous reset of the attribute data is not provided, said second subset being configured as an ordered n-tuple; means for designating, as one control value for controlling a reset operation, a second of the plural bit control data of the subset which has a predetermined position in the ordered n-tuple; and means for setting one binary value at a position other than said predetermined position in the ordered n-tuple of the subset and outputting a signal from said decode logic circuit to indicate reset of the attribute data in the attribute buffer only when said first bit is of a predetermined value.

Claim 17

An apparatus, included within a computer graphics system, for encoding and decoding plural bit control data, input to a decode logic circuit, comprising: means for controlling a class designation operation to indicate whether simultaneous reset of attribute data is provided for pixels in an attribute buffer in said computer graphics system by converting a first bit of said plural bit control data means for outputting a first subset of the plural bit control data from said decode logic circuit to control a window identification operation, said first subset being of a first class including said first bit for and being dependent upon a value thereof to indicate that simultaneous reset of the attribute data is provided, said first subset being configured as an ordered n-tuple; means for outputting a second subset of the plural bit control data from said decode logic circuit to control said windows identification operation, said second subset being of a second class including said first bit and being dependent upon the value thereof to indicate that simultaneous reset of the attribute data is not provided, said second subset being configured as an ordered n-tuple; means for designating, as one control value for controlling a reset operation, a second of the plural bit control data of the subset which has a predetermined position in the ordered n-tuple; and means for setting one binary value at a position other than said predetermined position in the ordered n-tuple of the subset and outputting a signal from said decode logic circuit to indicate reset of the attribute data in the attribute buffer only when said first bit is of a predetermined value.