EP0330007A2 — Functional cache memory chip architecture

Claim 1

Independent Claim 240 words

VLSI cache memory subsystem including, on-chip a single-port, late-select, cache array organized to be n-way set-associative said chip including a plurality of functionally integrated units on-chip with the cache array, characterized by a normal central processing unit (CPU) read access function including means for accessing the chip in a fast, "late-select" mode, which is n-way set-associative, in effectively one memory cycle for a read operation to the central processing unit (CPU), by an internal late-write function including means for allowing a central processing unit (CPU) "write" to said one of n accessed words in effectively one cycle, and by a cache reload function including means for providing a highly parallel multi-word store-back and reload operation to and from main memory, to reduce the reload time for a store-in cache organization, said reload function providing a nearly transparent, multiple word reload and including a Cache-Reload Buffer, a Store-Back Buffer and a load-thru mechanism all included on the chip for reloading, said such system further including two separate decoders integrated on the chip, one for normal single word read/write cache access by the central processing unit (CPU) and one for parallel multi-word cache reload, and means to access data in the Cache Reload Buffer (CRB) which has been transferred out of main memory to the chip but not yet reloaded into the cache array, said two decoders providing two different accessing modes required for central processing unit (CPU) or main memory operations.

Claim 2

Dependent Claim 240 words

VLSI cache memory subsystem including, on-chip a single-port, late-select, cache array organized to be n-way set-associative said chip including a plurality of functionally integrated units on-chip with the cache array, characterized by a normal central processing unit (CPU) read access function including means for accessing the chip in a fast, "late-select" mode, which is n-way set-associative, in effectively one memory cycle for a read operation to the central processing unit (CPU), by an internal late-write function including means for allowing a central processing unit (CPU) "write" to said one of n accessed words in effectively one cycle, and by a cache reload function including means for providing a highly parallel multi-word store-back and reload operation to and from main memory, to reduce the reload time for a store-in cache organization, said reload function providing a nearly transparent, multiple word reload and including a Cache-Reload Buffer, a Store-Back Buffer and a load-thru mechanism all included on the chip for reloading, said such system further including two separate decoders integrated on the chip, one for normal single word read/write cache access by the central processing unit (CPU) and one for parallel multi-word cache reload, and means to access data in the Cache Reload Buffer (CRB) which has been transferred out of main memory to the chip but not yet reloaded into the cache array, said two decoders providing two different accessing modes required for central processing unit (CPU) or main memory operations.

Claim 3

Dependent Claim 220 words

VLSI cache memory subsystem characterized by a chip including; n separate set-associative memory segments in the on-chip cache array, first addressing/decoding means interfacing the array with the central processing unit (CPU), comprising means for accessing first, n single logical words, one from each associative set in the array and for accessing next a single logical word from a single associative set from said n words as pointed to by the overall cache address presented to the system, second addressing/decoding means interfacing with the main memory for accessing an entire data block from a single associative set in the array, means utilizing said first addressing means for a normal cache read/write access, and means utilizing said second addressing means for memory store-back and cache reload operations, a late-write function which allows a word to be written into the array from the central processing unit (CPU) at one of n accessed words within a single memory cycle, control means including first buffers for interfacing logical words to be accessed to/from the cache and from/to the central processing unit (CPU) in a single array access cycle, and control means including second buffers for interfacing blocks to be accessed to/from main memory and from/to the cache for reading/writing multiple logical words of a single associative set's data block in a single array access cycle.

Claim 4

Dependent Claim 220 words

VLSI cache memory subsystem characterized by a chip including; n separate set-associative memory segments in the on-chip cache array, first addressing/decoding means interfacing the array with the central processing unit (CPU), comprising means for accessing first, n single logical words, one from each associative set in the array and for accessing next a single logical word from a single associative set from said n words as pointed to by the overall cache address presented to the system, second addressing/decoding means interfacing with the main memory for accessing an entire data block from a single associative set in the array, means utilizing said first addressing means for a normal cache read/write access, and means utilizing said second addressing means for memory store-back and cache reload operations, a late-write function which allows a word to be written into the array from the central processing unit (CPU) at one of n accessed words within a single memory cycle, control means including first buffers for interfacing logical words to be accessed to/from the cache and from/to the central processing unit (CPU) in a single array access cycle, and control means including second buffers for interfacing blocks to be accessed to/from main memory and from/to the cache for reading/writing multiple logical words of a single associative set's data block in a single array access cycle.

Claim 5

Dependent Claim 45 words

VLSI cache memory subsystem as set forth in Claim 2, first and second addressing/decoding means include a common portion for selecting a particular row in said array, said row including a multiple word data block for each of the n associative sets in said array.

Claim 6

Dependent Claim 70 words

VLSI cache memory subsystem chip as set forth in one of Claims 1 to 3 characterized by Store-Back Buffer means for temporarily storing a multiple-word data block accessed via said second addressing/decoding means and means for storing said data block in said Store-Back Buffer prior to transfer to the main memory, and by means for accessing said Store-Back Buffer means to transfer a block of data to the main memory.

Claim 7

Dependent Claim 78 words

VLSI cache memory subsystem chip as set forth in Claim 4 characterized by a Cache-Reload Buffer for storing a multi-word data block transferred from main memory for reloading into the cache array via said second addressing/decoding means, and by internal bus means on said chip having a band width equal to the complete multi-word data block to be accessed in a single associative set within said array connected between the array, the Store-Back Buffer and the Cache-Reload Buffer.

Claim 8

Dependent Claim 84 words

VLSI cache memory subsystem chip as set forth in Claim 5 characterized in that Cache-Reload Buffer includes control means including a reload address register and means for interrogating the contents of said register on every normal read/write cache access from the central processing unit (CPU) to determine if a requested data word is currently stored in said Cache-Reload Buffer, and means for accessing the addressed word in the Cache- Reload Buffer for read/write operations between the central processing unit (CPU) and the cache chip.

Claim 9

Dependent Claim 56 words

VLSI cache memory subsystem chip as set forth in Claim 2 characterized by a buffer as load-through means comprising a data path for transferring an addressed logical word directly from main memory to the central processing unit (CPU) externally of said array during reload when said logical word is transferred from main memory to the chip.

Claim 10

Dependent Claim 63 words

VLSI cache memory subsystem chip as set forth in Claim 4 characterized in that the late-select mechanism includes means for detecting a late-select timing signal to activate the late-select operating mode in the array and means for decoding the late-select signal to determine which associative set is to be selected for any central processing unit (CPU) access, main memory reload or store-back access.

Claim 11

Dependent Claim 297 words

VLSI cache memory subsystem chip as set forth in one of claims 1 to 8, characterized by n separate set-associative memory segments in the on-chip cache array, by first addressing/decoding means interfacing the array with the central processing unit (CPU), comprising means for accessing first, n single logical words, one from each associative set in the array and for accessing next, a single logical word from a single associative set from said n words as pointed to by the overall cache address presented to the system, by second addressing/decoding means interfacing with the main memory for accessing an entire data block from a single associative set in the array, whereby said first and second addressing/decoding means including a common portion for selecting a particular row in said array, said row including a multiple word data block for each of the n associative sets in said array, by means utilizing said first addressing means for a normal cache read/write access, and bymeans utilizing said second addressing means for highly parallel multi-word memory store-back and cache reload operations, by a late-write function which allows a word to be written into the array from the central processing unit (CPU) at one of n accessed words within a single memory cycle, by control means including first buffers for accumulating logical words to be accessed to/from the cache and from/to the central processing unit (CPU) in a single array access cycle, by control means including second buffers for accumulating blocks to be accessed to/from main memory and from/to the cache for reading/writing multiple logical words of a single associative set's data block in a single array access cycle, and by a late-select mechanism including means for providing a signal to said chip indicating which associative set is required for a particular access.

Claim 12

Dependent Claim 203 words

Cache memory subsystem as set forth in Claim 9 characterized by the reload data path includes a store-back buffer for temporarily storing a multiple word data block accessed via said second addressing/decoding means when it is determined that said data block has been altered, and means for storing said data block in said Store-Back Buffer prior to transfer to the main memory, and by means for accessing said Store-Back Buffer means to transfer data to the main memory, by a Cache-Reload Buffer for storing a multi-word data block transferred from main memory for loading into the cache array via said second addressing/decoding means, and by internal bus means on said chip having a band width equal to a complete multi-word data block to be accessed in a single associative set within said array connected between the array, the Store-Back Buffer and the Cache-Reload Buffer, and by control means associated with both said Cache-Reload Buffer and said Store-Back Buffer means to indicate when the Cache-Reload Buffer has been fully loaded from main memory and for indicating when the store-back buffer has transferred its complete contents to main memory and wherein the memory/cache bus has a narrower band width than said internal cache chip bus.

Claim 13

Dependent Claim 176 words

Cache memory subsystem chip as set forth in Claim 10 characterized by by load-thru means comprising a data path for transferring an addressed logical word directly from main memory to the central processing unit (CPU) externally of said array after the complete data block including said logical word is transferred from main memory to the chip, wherein the Cache-Reload Buffer includes control means including a reload address register and means for interrogating the contents of said register on every normal read/write cache access from the central processing unit (CPU) to determine if a requested data word is currently stored in said Cache-Reload Buffer, and by means for accessing the addressed word in the Cache-Reload Buffer for read/write operations between the central processing unit (CPU) and the cache chip, and wherein the late-select mechanism includes means for detecting a late-select timing signal to activate the late-select operating mode in the array and means for decoding the late-select signal to determine which associative set is to be selected from any CPU access, main memory reload or store-back access.

Functional cache memory chip architecture

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