Programmable video display character control circuit using multi-purpose RAM for display attributes, character generator, and refresh memory

Claim 1

A video display control circuit for an intelligent terminal of the type having a visual display, comprising: a general purpose microprocessor having an address bus and a data bus, an alphanumeric CRT controller for generating row addresses, refresh addresses and CRT timing signals coupled to said microprocessor buses, means for couping a random access memory (RAM) to said CRT controller and to said microprocessor buses, said RAM memory providing ASCII character data output in response to a refresh address input, means for coupling said ASCII character data output from said RAM to the input of said RAM to provide data output signals from said RAM, means for coupling said alphanumeric CRT controller to said RAM to simultaneously provide row address input information to be combined with said character data output from said RAM to define a unique memory location in said RAM containing video data output information, means for coupling a buffer register to said RAM for storing said data output information from said RAM in parallel form, means for coupling a shift register to said buffer register for serializing said parallel form video data output information in said buffer register, video output means coupled to said shift register and said visual display for generating signals indicative of dot signals to be displayed on said visual display, and means for coupling timing and memory control means to said RAM, to the CRT controller, to said microprocessor, and to said RAM for coordinating the transfer of said video data output information being transferred to said buffer register under program control of said microprocessor.