Patent US3473419A successfully refreshed from Google Patents.
EP0397995A2
Expired / Lapsed
EP
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Mixed size data cache status fields
Assignee: Motorola Solutions Inc
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Filing: 1990-03-23
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Granted: —
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Expires: 2010-03-23
Abstract
Abstract A data cache (16) capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache (16) coherent with memory (26), without writing the entire cache entry to memory (26), thereby reducing bus utilization. Each data cache entry is comprised of three items: data, a tag address, and a mixed size status field. The mixed size status fields provide one bit to indicate the validity of the data cache entry and multiple bits to indicate if the entry contains data that has not been written to memory (26) (dirtiness). Multiple dirty bits provide a data cache controller (14) with sufficient information to minimize the number of memory accesses used to unload a dirty entry. The data cache controller (14) uses the multiple dirty bits to determine the quantity and type of accesses required to write the dirty data to memory (26). The portions of the entry being replaced that are clean (unmodified) are not written to memory (26).
Inventors
- 👤 Robin Wayne Edenfield
- 👤 William B. Ledbetter, Jr.
- 👤 Russell A. Reininger
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 08:19
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
392 words
A data processing system (10), comprising: a data processor (12); a memory (26) for storing a plurality of data entries, identified by a plurality of memory addresses, and for providing said data entries to said processor; a first communications bus (24), for transferring said plurality of data entries between said memory (26) and said data processor (12), in response to a first control signal; a bus controller (20); a cache (16), coupled to said memory (26) and said data processor (12), for storing in each of a plurality of cache lines an addressable data cache entry containing a plurality of bits of data, for receiving from said data processor (12) a modified data entry, in a first write mode, and for transferring at least one of said plurality of bits of said addressable data cache entry to said memory (26), in a second write mode, said cache (16) comprising: register means (36, 38, 40, 42) for storing in each of said plurality of cache lines said addressable data cache entry containing said plurality of bits of data, and for storing a first state entry, indicating that said cache line is valid, and a second state entry corresponding to each of said plurality of bits of data, indicating said plurality of bits of data is consistent or inconsistent with a data entry at a memory address corresponding to said addressable data cache entry; first means (22), coupled to said cache (16) and said bus controller (20), for receiving said modified data entry from said cache (16) and transferring said modified data entry to said memory (26), when said corresponding second state entry indicates that said plurality of bits of data is inconsistent with said data entry at said memory address corresponding to said addressable data cache entry, and for receiving a plurality of replacement data entries from said memory (26), and transferring said replacement data entries to said register means (36, 38, 40, 42); and cache controller means (14), coupled to said first means (22), and said register means (36, 38, 40, 42), for reading said second state entry corresponding to each of said plurality of bits of data, for controlling the transfer of said modified data entry to said memory (26), and for controlling the transfer of said plurality of replacement data entries from said first means (22) to said cache (16).
Claim 2
Dependent Claim
392 words
A data processing system (10), comprising: a data processor (12); a memory (26) for storing a plurality of data entries, identified by a plurality of memory addresses, and for providing said data entries to said processor; a first communications bus (24), for transferring said plurality of data entries between said memory (26) and said data processor (12), in response to a first control signal; a bus controller (20); a cache (16), coupled to said memory (26) and said data processor (12), for storing in each of a plurality of cache lines an addressable data cache entry containing a plurality of bits of data, for receiving from said data processor (12) a modified data entry, in a first write mode, and for transferring at least one of said plurality of bits of said addressable data cache entry to said memory (26), in a second write mode, said cache (16) comprising: register means (36, 38, 40, 42) for storing in each of said plurality of cache lines said addressable data cache entry containing said plurality of bits of data, and for storing a first state entry, indicating that said cache line is valid, and a second state entry corresponding to each of said plurality of bits of data, indicating said plurality of bits of data is consistent or inconsistent with a data entry at a memory address corresponding to said addressable data cache entry; first means (22), coupled to said cache (16) and said bus controller (20), for receiving said modified data entry from said cache (16) and transferring said modified data entry to said memory (26), when said corresponding second state entry indicates that said plurality of bits of data is inconsistent with said data entry at said memory address corresponding to said addressable data cache entry, and for receiving a plurality of replacement data entries from said memory (26), and transferring said replacement data entries to said register means (36, 38, 40, 42); and cache controller means (14), coupled to said first means (22), and said register means (36, 38, 40, 42), for reading said second state entry corresponding to each of said plurality of bits of data, for controlling the transfer of said modified data entry to said memory (26), and for controlling the transfer of said plurality of replacement data entries from said first means (22) to said cache (16).
Claim 3
Dependent Claim
53 words
The data processing system of claim 1 wherein said cache (16) stores said modified data entry received from said processor (12) in at least one of said plurality of cache lines, when said modified data entry has an address which matches an address of at least one of said plurality of cache lines.
Claim 4
Dependent Claim
29 words
The data processing system of claim 1 wherein said bus controller (20) is coupled to said first communications bus (24), said cache (16), and said cache controller means (14).
Claim 5
Dependent Claim
73 words
The data processing system (10) of claim 1 wherein said first means (22) for transferring at least one of said plurality of bits to said memory, comprises buffer means, coupled to said bus controller (20), for storing said replacement data entry received from said memory (26), in a first mode of operation, and for storing at least one of said plurality of bits received from said cache, in a second mode of operation.
Claim 6
Dependent Claim
55 words
The data processing system (10) of claim 1 wherein said cache controller means (14) receives a plurality of control signals from said bus controller (20) and said processor (12), and controls the transfer of data between said cache (16), said bus controller (20) and said processor (12), in response to said plurality of control signals.
Claim 7
Dependent Claim
366 words
In a data processing system (10) having a cache (16) for storing a plurality of addressable data entries in a plurality of cache lines, with each of said plurality of addressable data entries containing a plurality of bits of data, a first status entry, indicating the validity of said cache line, and a second status entry, indicating the consistency of each of said plurality of bits of data with a data entry contained in a memory (26) at a corresponding memory address, and for selectively transferring at least one of said plurality of bits of data to said memory (26), via a communications bus (24), when at least one of said plurality of bits of data is inconsistent with said data entry contained in said corresponding memory address, said cache (16) comprising: register means (36, 38, 40, 42) for storing each of said plurality of addressable data entries, with each of said plurality of addressable data entries being a copy of said data entry contained in said memory (26) at said corresponding memory address; means, coupled to said register means (36, 38, 40, 42), for transferring at least one of said plurality of bits of data to said memory (26), when said second state entry indicates that at least one of said plurality of bits of data is inconsistent with said data entry at said corresponding memory address, and for receiving a plurality of replacement data entries from said memory (26) to update said cache line, comprising: buffer means (22) for temporarily storing at least one of said plurality of bits of data, for transfer to said memory (26), in a first mode, and for temporarily storing a replacement data cache entry, received from said memory (26), in a second mode; and control means (14), coupled to said register means, for enabling and disabling said cache (16), and for providing a plurality of control signals to a bus controller (20), thereby signalling said bus controller (20) to transfer said plurality of bits of data from said cache (16) to said memory (26), in said first mode, and to transfer said replacement data cache entry from said memory (26) to said cache (16), in said second mode.
Claim 8
Dependent Claim
366 words
In a data processing system (10) having a cache (16) for storing a plurality of addressable data entries in a plurality of cache lines, with each of said plurality of addressable data entries containing a plurality of bits of data, a first status entry, indicating the validity of said cache line, and a second status entry, indicating the consistency of each of said plurality of bits of data with a data entry contained in a memory (26) at a corresponding memory address, and for selectively transferring at least one of said plurality of bits of data to said memory (26), via a communications bus (24), when at least one of said plurality of bits of data is inconsistent with said data entry contained in said corresponding memory address, said cache (16) comprising: register means (36, 38, 40, 42) for storing each of said plurality of addressable data entries, with each of said plurality of addressable data entries being a copy of said data entry contained in said memory (26) at said corresponding memory address; means, coupled to said register means (36, 38, 40, 42), for transferring at least one of said plurality of bits of data to said memory (26), when said second state entry indicates that at least one of said plurality of bits of data is inconsistent with said data entry at said corresponding memory address, and for receiving a plurality of replacement data entries from said memory (26) to update said cache line, comprising: buffer means (22) for temporarily storing at least one of said plurality of bits of data, for transfer to said memory (26), in a first mode, and for temporarily storing a replacement data cache entry, received from said memory (26), in a second mode; and control means (14), coupled to said register means, for enabling and disabling said cache (16), and for providing a plurality of control signals to a bus controller (20), thereby signalling said bus controller (20) to transfer said plurality of bits of data from said cache (16) to said memory (26), in said first mode, and to transfer said replacement data cache entry from said memory (26) to said cache (16), in said second mode.
Claim 9
Dependent Claim
44 words
The data processing system (10) of claim 5 further comprising a processor (12) coupled to said control means, for supplying said plurality of addressable data entries to said cache, and for modifying said second status entry, of said appropriate plurality of bits of data.
Claim 10
Dependent Claim
46 words
The data processing system (10) of claim 6 wherein said processor (12) changes the status of said second state entry to notify said control means that upon replacement at least one of said plurality of bits must be transferred to said memory, in said first mode.
Claim 11
Dependent Claim
354 words
A cache memory system, for storing a plurality of addressable data cache entries in a plurality of cache lines, with each of said plurality of addressable data cache entries containing a plurality of bits of data, a first status entry, indicating the validity of said cache line, and a second status entry, indicating the consistency of each of said plurality of data bits with a data entry contained in a memory (26) at a corresponding memory address, and for selectively transferring at least one of said plurality of bits of data to said memory (26), via a communications bus (24), when at least one of said plurality of bits of data is inconsistent with said data entry contained in said corresponding memory address, said cache memory system, comprising: register means (36, 38, 40, 42) for storing each of said plurality of addressable data cache entries, with each of said plurality of addressable data cache entries being a copy of said data entry contained in said memory (26) at said corresponding memory address; means for transferring at least one of said plurality of bits of data to said memory (26), when said second state entry indicates that at least one of said plurality of bits of data is inconsistent with with said data entry at said corresponding memory address, and for receiving a plurality of replacement data entries from said memory (26) to update said cache line, comprising: buffer means (22) for temporarily storing at least one of said plurality of bits of data, for transfer to said memory, in a first mode, and for temporarily storing a replacement data cache entry, received from said memory, in a second mode; and control means (14), coupled to said register means, for enabling and disabling said cache (16), and for providing a plurality of control signals to a bus controller (20), thereby signalling said bus controller (20) to transfer said plurality of bits of data from said cache (16) to said memory (26), in a first mode, and to transfer said replacement data cache entry from said memory (26) to said cache (16), in said second mode.
Claim 12
Dependent Claim
354 words
A cache memory system, for storing a plurality of addressable data cache entries in a plurality of cache lines, with each of said plurality of addressable data cache entries containing a plurality of bits of data, a first status entry, indicating the validity of said cache line, and a second status entry, indicating the consistency of each of said plurality of data bits with a data entry contained in a memory (26) at a corresponding memory address, and for selectively transferring at least one of said plurality of bits of data to said memory (26), via a communications bus (24), when at least one of said plurality of bits of data is inconsistent with said data entry contained in said corresponding memory address, said cache memory system, comprising: register means (36, 38, 40, 42) for storing each of said plurality of addressable data cache entries, with each of said plurality of addressable data cache entries being a copy of said data entry contained in said memory (26) at said corresponding memory address; means for transferring at least one of said plurality of bits of data to said memory (26), when said second state entry indicates that at least one of said plurality of bits of data is inconsistent with with said data entry at said corresponding memory address, and for receiving a plurality of replacement data entries from said memory (26) to update said cache line, comprising: buffer means (22) for temporarily storing at least one of said plurality of bits of data, for transfer to said memory, in a first mode, and for temporarily storing a replacement data cache entry, received from said memory, in a second mode; and control means (14), coupled to said register means, for enabling and disabling said cache (16), and for providing a plurality of control signals to a bus controller (20), thereby signalling said bus controller (20) to transfer said plurality of bits of data from said cache (16) to said memory (26), in a first mode, and to transfer said replacement data cache entry from said memory (26) to said cache (16), in said second mode.
References Cited (Backward Citations)
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