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US5387823A Expired / Lapsed US ⏱️ 0.0 years remaining

Fuse-programmable redundancy control circuit

Assignee: Lapis Semiconductor Co Ltd
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Filing: 1993-10-05
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Granted: 1995-02-07
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Expires: 2013-10-05
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Abstract

Abstract A fuse-programmable control circuit has a master control circuit with a first fusible link that controls the feeding of power to a fuse-programmable memory. If output of signals from the fuse-programmable memory is not required, the first fusible link is cut. If output of signals from the fuse-programmable memory is required, the first fusible link is left uncut and the fuse-programmable memory is programmed by cutting one fusible link in each of a number of pairs of fusible links. In either case, no current can flow through the fuse-programmable control circuit.

Inventors

  • 👤 Yuichi Ashizawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 08:20
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; H; H10; H10D; H10D84/00; H10D84/01

Claims Analysis

Total Claims: 23
Claim 1
Independent Claim 175 words
A fuse-programmable control circuit for generating fuse-programmable signals in an integrated circuit, comprising: a master control circuit having two fusible links coupled in series between a first potential and a second potential, for generating a control signal from a point between said two fusible links, one of said two fusible links being cut to activate said control signal if said fuse-programmable signals are required, and another of said two fusible links being cut to deactivate said control signal if said fuse-programmable signals are not required; a switching element controlled by said control signal, coupled to supply said first potential when switched on by said control signal; and a fuse-programmable memory having a plurality of pairs of fusible links, each pair coupled in series between said switching element and said second potential, and a like plurality of output terminals, each output terminal disposed between the fusible links in a corresponding pair, for generating said fuse-programmable signals from said output terminals by cutting of one or another of the fusible links in respective pairs of fusible links.
Claim 2
Dependent Claim 175 words
A fuse-programmable control circuit for generating fuse-programmable signals in an integrated circuit, comprising: a master control circuit having two fusible links coupled in series between a first potential and a second potential, for generating a control signal from a point between said two fusible links, one of said two fusible links being cut to activate said control signal if said fuse-programmable signals are required, and another of said two fusible links being cut to deactivate said control signal if said fuse-programmable signals are not required; a switching element controlled by said control signal, coupled to supply said first potential when switched on by said control signal; and a fuse-programmable memory having a plurality of pairs of fusible links, each pair coupled in series between said switching element and said second potential, and a like plurality of output terminals, each output terminal disposed between the fusible links in a corresponding pair, for generating said fuse-programmable signals from said output terminals by cutting of one or another of the fusible links in respective pairs of fusible links.
Claim 3
Dependent Claim 23 words
The circuit of claim 1, wherein said fuse-programmable signals are used to select redundant elements to replace defective elements of said integrated circuit.
Claim 4
Dependent Claim 36 words
The circuit of claim 1, wherein said master control circuit also has a current-limiting element coupled in series with said two fusible links, for limiting current flow when neither of said two fusible links is cut.
Claim 5
Dependent Claim 17 words
The circuit of claim 3, wherein said current-limiting element is a transistor that is permanently switched on.
Claim 6
Dependent Claim 20 words
The circuit of claim 3, wherein said current-limiting element is disposed between said first potential and said two fusible links.
Claim 7
Dependent Claim 20 words
The circuit of claim 3, wherein said current-limiting element is disposed between said second potential and said two fusible links.
Claim 8
Dependent Claim 46 words
The circuit of claim 1, wherein said switching element is a field-effect transistor with a gate electrode coupled to receive said control signal, a source electrode coupled to said first potential, and a drain electrode coupled to the pairs of fusible links in said fuse-programmable memory.
Claim 9
Dependent Claim 25 words
The circuit of claim 1, wherein said master control circuit also has an inverter coupled to said two fusible links for inverting said control signal.
Claim 10
Dependent Claim 119 words
A fuse-programmable control circuit for generating fuse-programmable signals in an integrated circuit, comprising: a master control circuit having a first fusible link coupled to a first potential, said first fusible link being cut if said fuse-programmable signals are not required, and left uncut if said fuse-programmable signals are required; and a fuse-programmable memory having a plurality of pairs of fusible links, each pair coupled in series between said first fusible link and a second potential, and a like plurality of output terminals, each output terminal disposed between the fusible links in a corresponding pair, for generating said fuse-programmable signals from said output terminals by cutting of one or another of the fusible links in respective pairs of fusible links.
Claim 11
Dependent Claim 119 words
A fuse-programmable control circuit for generating fuse-programmable signals in an integrated circuit, comprising: a master control circuit having a first fusible link coupled to a first potential, said first fusible link being cut if said fuse-programmable signals are not required, and left uncut if said fuse-programmable signals are required; and a fuse-programmable memory having a plurality of pairs of fusible links, each pair coupled in series between said first fusible link and a second potential, and a like plurality of output terminals, each output terminal disposed between the fusible links in a corresponding pair, for generating said fuse-programmable signals from said output terminals by cutting of one or another of the fusible links in respective pairs of fusible links.
Claim 12
Dependent Claim 23 words
The circuit of claim 9, wherein said fuse-programmable signals are used to select redundant elements to replace defective elements of said integrated circuit.
Claim 13
Dependent Claim 35 words
The circuit of claim 9, wherein said master control circuit also has a current-limiting element coupled in series with said first fusible link between said first potential and the fusible links in said fuse-programmable memory.
Claim 14
Dependent Claim 20 words
The circuit of claim 11, wherein said current-limiting element is disposed between said first potential and said first fusible link.
Claim 15
Dependent Claim 17 words
The circuit of claim 11, wherein said current-limiting element is a transistor that is permanently switched on.
Claim 16
Dependent Claim 33 words
The circuit of claim 9, wherein a control signal for indicating whether said fuse-programmable signals are valid or invalid is output from a point between said first fusible link and said fuse-programmable memory.
Claim 17
Independent Claim 99 words
A method of generating fuse-programmable signals in an integrated circuit, comprising the steps of: if said fuse-programmable signals are required, programming them by cutting one fusible link in each of a plurality of pairs of fusible links in a fuse-programmable memory; if said fuse-programmable signals are required, leaving a first fusible link uncut, thereby supplying power to said fuse-programmable memory; if said fuse-programmable signals are not required, leaving the pairs of fusible links in said fuse-programmable memory uncut; and if said fuse-programmable signals are not required, cutting said first fusible link, thereby cutting off power to said fuse-programmable memory.
Claim 18
Independent Claim 99 words
A method of generating fuse-programmable signals in an integrated circuit, comprising the steps of: if said fuse-programmable signals are required, programming them by cutting one fusible link in each of a plurality of pairs of fusible links in a fuse-programmable memory; if said fuse-programmable signals are required, leaving a first fusible link uncut, thereby supplying power to said fuse-programmable memory; if said fuse-programmable signals are not required, leaving the pairs of fusible links in said fuse-programmable memory uncut; and if said fuse-programmable signals are not required, cutting said first fusible link, thereby cutting off power to said fuse-programmable memory.
Claim 19
Dependent Claim 23 words
The method of claim 15, wherein said fuse-programmable signals are used to select redundant elements to replace defective elements of said integrated circuit.
Claim 20
Dependent Claim 18 words
The method of claim 15, wherein power is fed to said fuse-programmable memory through said first fusible link.
Claim 21
Dependent Claim 36 words
The method of claim 17, comprising the further step of generating a control signal, indicating whether said fuse-programmable signals are valid or invalid, from a point between said first fusible link and said fuse-programmable memory .
Claim 22
Dependent Claim 66 words
The method of claim 15, comprising the further steps of: if said fuse-programmable signals are required, cutting a second fusible link coupled in series with said first fusible link; generating a control signal from a point between said first fusible link and said second fusible link; using said control signal to control a switching element; and feeding power through said switching element to said fuse-programmable memory.
Claim 23
Dependent Claim 24 words
The method of claim 19, comprising the further step of using said control signal to indicate whether said fuse-programmable signals are valid or invalid.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-02-06 1998-08-08 1999-02-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-02-06 2002-08-08 2003-02-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-02-06 2006-08-08 2007-02-07 $7700.00 Window Closed / Lapsed

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