Redundant control circuit incorporated in semiconductor integrated circuit device for producing control signal indicative of replacement with redundant unit

Claim 2

A redundant control circuit associated with a redundant component circuit replaceable with a defective component circuit, comprising: a) a programming unit for storing a defective address assigned to said defective component circuit, and operative to compare said defective address with an external address supplied externally thereof to determine whether or not said defective component circuit is selected, said programming unit blocking an output signal line from a discharge line for shifting a redundant control signal on said output signal line to an active level when said external address is consistent with said defective address stored therein, said programming unit providing a current path from said output signal line to said discharge line when said external address is inconsistent with said defective address for shifting said redundant control signal to an inactive level; b) a precharging unit operative to precharge said output signal line to said active level before arrival of said external address at said programming unit, and providing an emergency current path to said output signal line for maintaining said output signal line at said active level even if a current path is established between said output signal line and said discharge line in the presence of said external address consistent with said defective address, said precharging unit blocking said emergency current path in the presence of said external address inconsistent with said defective address; and c) a make-up unit operative to replenish current to said output signal line when said output signal line is in the inactive level.

Claim 3

A redundant control circuit as set forth in claim 1, in which said programming unit comprises a plurality of series combinations of breakable fuse elements and enhancement type switching transistors gated by internal address bits and the complementary bits thereof indicative of said external address, said plurality of series combinations being coupled in parallel between said output signal line and said discharge line.

Claim 4

A redundant control circuit as set forth in claim 2, in which said make-up unit comprises c-1) an inverter having an input node coupled with said output signal line for producing a first activation signal, and c-2) an enhancement type make-up transistor coupled between a source of current and said output signal line and responsive to said first activation signal.

Claim 5

A redundant control circuit associated with a redundant component circuit replaceable with a defective component circuit, comprising: a) a programming unit for storing a defective address assigned to said defective component circuit, and operative to compare said defective address with an external address supplied externally thereof to determine whether or not said defective component circuit is selected, said programming unit blocking an output signal line from a discharge line for shifting a redundant control signal on said output signal line to an active level when said external address is consistent with said defective address stored therein, said programming unit providing a current path from said output signal line to said discharge line when said external address is inconsistent with said defective address for shifting said redundant control signal to an inactive level, said programming unit comprising: a-1) a plurality of series combinations of breakable fuse elements and enhancement type switching transistors gated by internal address bits and the complementary bits thereof indicative of said external address, said plurality of series combinations being coupled in parallel between said output signal line and said discharge line; b) a precharging unit operative to precharge said output signal line to said active level before arrival of said external address at said programming level even if a current path is established between said output signal line and said discharge line in the presence of said external address consistent with said defective address, said precharging unit comprising: b-1) a first inverter supplied with a first activation signal for producing a first enable signal, b-2) a first NAND gate supplied with said first enable signal and a level retaining signal for producing a second enable signal, b-3) a second MAMD gate supplied with said second enable signal and a precharge control signal for producing a complementary signal of a second activation signal, b-4) a second inverter supplied with said complementary signal for producing the second activation signal, and b-5) an enhancement type precharging transistor coupled with a source of current to said output signal line and responsive to said second activation signal; c) a make-up unit operative to replenish current to said output signal line when said output signal line is in the inactive level, said make-up unit comprising: c-1) a third inverter having an input node coupled with said output signal line for producing said first activation signal, and c-2) an enhancement type make-up transistor coupled between said source of current and said output signal line and responsive to said first activation signal.

Claim 6

A redundant control circuit associated with a redundant component circuit replaceable with a defective component circuit, comprising: a) a programming unit for storing a defective address assigned to said defective component circuit, and operative to compare said defective address with an external address supplied externally thereof to determine whether or not said defective component circuit is selected, said programming unit blocking an output signal line from a discharge line for shifting a redundant control signal on said output signal line to an active level when said external address is consistent with said defective address stored therein, said programming unit providing a current path from said output signal line to said discharge line when said external address is inconsistent with said defective address for shifting said redundant control signal to an inactive level, said programming unit comprising: a-1) a plurality of series combinations of breakable fuse elements and enhancement type switching transistors gated by internal address bits and the complementary bits thereof indicative of said external address, said plurality of series combinations being coupled in parallel between said output signal line and said discharge line; b) a precharging unit operative to precharge said output signal line to said active level before arrival of said external address at said programming level even if a current path is established between said output signal line and said discharge line in the presence of said external address consistent with said defective address, said precharging unit comprising: b-1) a first inverter supplied with a first activation signal for producing a first enable signal, b-2) a first NAND gate supplied with said first enable signal and a level retaining signal for producing a second enable signal, b-3) a second MAMD gate supplied with said second enable signal and a precharge control signal for producing a complementary signal of a second activation signal, b-4) a second inverter supplied with said complementary signal for producing the second activation signal, and b-5) an enhancement type precharging transistor coupled with a source of current to said output signal line and responsive to said second activation signal; c) a make-up unit operative to replenish current to said output signal line when said output signal line is in the inactive level, said make-up unit comprising: c-1) a third inverter having an input node coupled with said output signal line for producing said first activation signal, and c-2) an enhancement type make-up transistor coupled between said source of current and said output signal line and responsive to said first activation signal.