Method for making a fillet for integrated circuit metal plug

Claim 1

A method of fabricating a semiconductor device comprising the steps of: providing a semiconductor wafer having an upper surface; forming a well having a depth in said upper surface; completely filling said well and covering said upper surface with a blanket metal deposition; overetching said blanket metal to completely remove said blanket metal from said upper surface and from an upper portion of said well to provide a metal plug partially filling said well, said upper portion being up to fifteen percent of the depth of said well; completely filling said upper portion of said well with doped silicon to provide a smooth electrical contact surface that is planar with said upper surface.

Claim 2

A method of fabricating a semiconductor device comprising the steps of: providing a semiconductor wafer having an upper surface; forming a well having a depth in said upper surface; completely filling said well and covering said upper surface with a blanket metal deposition; overetching said blanket metal to completely remove said blanket metal from said upper surface and from an upper portion of said well to provide a metal plug partially filling said well, said upper portion being up to fifteen percent of the depth of said well; completely filling said upper portion of said well with doped silicon to provide a smooth electrical contact surface that is planar with said upper surface.

Claim 10

A method of fabricating a semiconductor device comprising the steps of: providing a semiconductor wafer having an upper surface; forming a well having a depth in said upper surface; depositing a blanket of metal to overfill said well and cover said upper surface, said blanket of metal being more conductive than polysilicon; etching said blanket of metal to expose said upper surface and provide a metal plug only partially filling said well, wherein said metal plug includes an irregular upper surface; creating a layer of doped silicon having a lower surface filling irregularities in said irregular surface of said metal plug and having a smooth upper surface planar with said upper surface of said semiconductor wafer, said layer of doped silicon forming a fillet; forming a conductive layer making electrical contact with said upper surface of said fillet.

Claim 11

A method of fabricating a semiconductor device comprising the steps of: providing a semiconductor wafer having an upper surface; forming a well having a depth in said upper surface; depositing a blanket of metal to overfill said well and cover said upper surface, said blanket of metal being more conductive than polysilicon; etching said blanket of metal to expose said upper surface and provide a metal plug only partially filling said well, wherein said metal plug includes an irregular upper surface; creating a layer of doped silicon having a lower surface filling irregularities in said irregular surface of said metal plug and having a smooth upper surface planar with said upper surface of said semiconductor wafer, said layer of doped silicon forming a fillet; forming a conductive layer making electrical contact with said upper surface of said fillet.

Claim 13

A method of fabricating a semiconductor device comprising the steps of: providing a semiconductor wafer having an upper surface; forming a well in said upper surface; lining said well with a titanium nitride (TIN) diffusion barrier; depositing a blanket metal layer over said diffusion barrier, wherein the step of depositing fills said well and covers said upper surface with said blanket metal layer; etching said blanket metal layer to completely remove said blanket metal layer from said upper surface and from an upper portion of said well to provide a metal plug partially filling said well, wherein the etching step provides a first irregularity on an upper portion of said metal plug and a second irregularity at a junction of said TiN diffusion barrier with said metal plug; filling said first and second irregularities with doped polysilicon using a low pressure chemical vapor deposition process to provide a smooth electrical contact surface; and planarizing said doped polysilicon.

Claim 14

A method of fabricating a semiconductor device comprising the steps of: providing a semiconductor wafer having an upper surface; forming a well in said upper surface; lining said well with a titanium nitride (TIN) diffusion barrier; depositing a blanket metal layer over said diffusion barrier, wherein the step of depositing fills said well and covers said upper surface with said blanket metal layer; etching said blanket metal layer to completely remove said blanket metal layer from said upper surface and from an upper portion of said well to provide a metal plug partially filling said well, wherein the etching step provides a first irregularity on an upper portion of said metal plug and a second irregularity at a junction of said TiN diffusion barrier with said metal plug; filling said first and second irregularities with doped polysilicon using a low pressure chemical vapor deposition process to provide a smooth electrical contact surface; and planarizing said doped polysilicon.

Claim 15

A method of fabricating a semiconductor devise comprising the steps of: providing a semiconductor wafer having an upper surface; forming a well having a high aspect ratio in said upper surface; lining said well and said upper surface with a titanium nitride (TIN) diffusion barrier; depositing a blanket metal layer having a greater conductivity than polysilicon over said diffusion barrier, wherein the step of depositing fills said well, covers said upper surface with said blanket metal layer, and forms an internal keyhole in said blanket metal layer; overetching so as to remove all of said blanket metal layer and said diffusion barrier from said upper surface and from an upper portion of said well to provide a metal plug partially filling said well, said upper portion being up to fifteen percent of the depth of said well wherein the overetching step exposes a keyhole irregularity on an upper portion of said metal plug and a barrier fang irregularity at a junction of said TiN diffusion barrier with said metal plug; and filling said keyhole and barrier fang irregularities and said upper portion of said well with doped silicon to provide a smooth electrical contact surface that is planar with said upper surface of said semiconductor substrate.

Claim 16

A method of fabricating a semiconductor devise comprising the steps of: providing a semiconductor wafer having an upper surface; forming a well having a high aspect ratio in said upper surface; lining said well and said upper surface with a titanium nitride (TIN) diffusion barrier; depositing a blanket metal layer having a greater conductivity than polysilicon over said diffusion barrier, wherein the step of depositing fills said well, covers said upper surface with said blanket metal layer, and forms an internal keyhole in said blanket metal layer; overetching so as to remove all of said blanket metal layer and said diffusion barrier from said upper surface and from an upper portion of said well to provide a metal plug partially filling said well, said upper portion being up to fifteen percent of the depth of said well wherein the overetching step exposes a keyhole irregularity on an upper portion of said metal plug and a barrier fang irregularity at a junction of said TiN diffusion barrier with said metal plug; and filling said keyhole and barrier fang irregularities and said upper portion of said well with doped silicon to provide a smooth electrical contact surface that is planar with said upper surface of said semiconductor substrate.