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US5386524A Expired / Lapsed US ⏱️ 0.0 years remaining

System for accessing information in a data processing system

Assignee: Hewlett Packard Development Co LP
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Filing: 1992-04-16
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Granted: 1995-01-31
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Expires: 2012-04-16
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Abstract

Abstract A memory mapping system for use by a port adapter in a computer facilitates access to named data buffers in host memory. The system generally comprises a mechanism that enables the adapter to efficiently translate the data buffer name to physical address locations in host memory without knowledge of the memory management policies of the computer. Specifically, the system includes various data structures and pointers that allow the port adapter to view host memory in "port pages" when accessing memory locations of a named data buffer. The data locations are virtually, but not physically, contiguous and the invention provides efficient identification of the physical addresses of the locations.

Inventors

  • 👤 Richard Lary
  • 👤 Robert Willard
  • 👤 Catharine van Ingen
  • 👤 David Thiel
  • 👤 William Watson
  • 👤 Barry Rubinson
  • 👤 Verell Boaen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 09:05
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 175 words
A system for accessing data located in a host memory comprising: at least one named data buffer containing addressable storage locations in said host memory; a first addressable storage region for storing a plurality of descriptors, each descriptor containing physical address information identifying the location of one of said at least one named data buffer in said host memory; a second addressable storage region including a location for storing a starting address of said first addressable storage region; and a processor located within a port adapter for determining the location of a selected descriptor in response to said starting address and an index contained within a command received by said port adapter, said index identifying said selected descriptor located in said first addressable storage region, said processor also determining the location of said data in a selected one of said at least one named data buffer in response to said physical address information contained in said selected descriptor, such that said port adapter accesses said data from non-contiguous addressable storage locations in said host memory.
Claim 2
Independent Claim 175 words
A system for accessing data located in a host memory comprising: at least one named data buffer containing addressable storage locations in said host memory; a first addressable storage region for storing a plurality of descriptors, each descriptor containing physical address information identifying the location of one of said at least one named data buffer in said host memory; a second addressable storage region including a location for storing a starting address of said first addressable storage region; and a processor located within a port adapter for determining the location of a selected descriptor in response to said starting address and an index contained within a command received by said port adapter, said index identifying said selected descriptor located in said first addressable storage region, said processor also determining the location of said data in a selected one of said at least one named data buffer in response to said physical address information contained in said selected descriptor, such that said port adapter accesses said data from non-contiguous addressable storage locations in said host memory.
Claim 3
Dependent Claim 18 words
The system of claim 1 wherein said first addressable storage region is a contiguous array of buffer descriptors.
Claim 4
Dependent Claim 21 words
The system of claim 2 wherein said second addressable storage region is an adapter block comprised of contiguous addressable storage locations.
Claim 5
Dependent Claim 303 words
A memory mapping system for apportioning a host memory into a plurality of port pages for use by a port adapter when accessing data in said host memory, said memory mapping system comprising: at least one named data buffer comprising addressable storage locations in said host memory; first contiguous storage means for storing a plurality of buffer descriptors, each buffer descriptor containing physical address information and physical offset information identifying the location of one of said at least one named data buffer in said host memory; second contiguous storage means for storing a plurality of buffer descriptor pointers, each buffer descriptor pointer containing a first starting address of said first contiguous storage means in said host memory; third contiguous storage means located in said host memory for storing a second starting address of said second contiguous storage means in said host memory; and processor means located within said port adapter for determining the location of said data in a selected one of said at least one named data buffer in response to said physical address information and said physical offset information contained in a selected buffer descriptor, said processor means further comprising: (i) means for determining the location of a selected buffer descriptor pointer in response to said second starting address and a first index, said first index contained within a message and identifying said selected buffer descriptor pointer stored in said second contiguous storage means; (ii) means for determining the location of said selected buffer descriptor in response to said first starting address and a second index, said second index contained within said message and identifying said selected buffer descriptor stored in said first contiguous storage means, such that said port adapter accesses said data from non-contiguous addressable storage locations of said at least one named data buffer in said host memory.
Claim 6
Dependent Claim 303 words
A memory mapping system for apportioning a host memory into a plurality of port pages for use by a port adapter when accessing data in said host memory, said memory mapping system comprising: at least one named data buffer comprising addressable storage locations in said host memory; first contiguous storage means for storing a plurality of buffer descriptors, each buffer descriptor containing physical address information and physical offset information identifying the location of one of said at least one named data buffer in said host memory; second contiguous storage means for storing a plurality of buffer descriptor pointers, each buffer descriptor pointer containing a first starting address of said first contiguous storage means in said host memory; third contiguous storage means located in said host memory for storing a second starting address of said second contiguous storage means in said host memory; and processor means located within said port adapter for determining the location of said data in a selected one of said at least one named data buffer in response to said physical address information and said physical offset information contained in a selected buffer descriptor, said processor means further comprising: (i) means for determining the location of a selected buffer descriptor pointer in response to said second starting address and a first index, said first index contained within a message and identifying said selected buffer descriptor pointer stored in said second contiguous storage means; (ii) means for determining the location of said selected buffer descriptor in response to said first starting address and a second index, said second index contained within said message and identifying said selected buffer descriptor stored in said first contiguous storage means, such that said port adapter accesses said data from non-contiguous addressable storage locations of said at least one named data buffer in said host memory.
Claim 7
Dependent Claim 33 words
The system of claim 4 wherein said physical address information contained in said buffer descriptor is a root pointer containing the physical starting location of a selected port page of said host memory.
Claim 8
Dependent Claim 50 words
The system of claim 5 wherein said physical offset information contained in said buffer descriptor is used by said processor means to determine the physical starting location of said data stored in said at least one named data buffer relative to the physical starting location of said selected port page.
Claim 9
Dependent Claim 50 words
The system of claim 4 wherein said physical address information contained in said buffer descriptor is a root pointer containing the physical starting location of an array of first pointers, each of which contain the physical starting location of one of said plurality of port pages of said host memory.
Claim 10
Dependent Claim 31 words
The system of claim 7 wherein said physical offset information contained in said buffer descriptor is used by said processor means to determine the physical address of a selected first pointer.
Claim 11
Dependent Claim 68 words
The system of claim 4 wherein said physical address information contained in said buffer descriptor is a root pointer containing the physical starting location of an array of second pointers, each of said second pointers containing the physical starting location of an array of first pointers, each of said first pointers containing the physical starting location of one of said plurality of port pages of said host memory.
Claim 12
Dependent Claim 57 words
The system of claim 4 wherein said physical address information contained in said buffer descriptor is a root pointer containing the physical starting location of an array of third pointer pairs, each of said third pointer pairs containing the physical starting location of a segment of said at least one named data buffer in said host memory.
Claim 13
Dependent Claim 332 words
In a data processing system including an external node coupled to a host computer including a central processing unit (CPU), a host memory and an I/O port adapter, a mapping method for apportioning said host memory into a plurality of port pages for use by said port adapter when accessing data stored in named data buffers in said host memory in response to a message received from one of said CPU and said external node, said named data buffers generally comprising addressable storage locations in said host memory, said mapping method comprising the steps of: storing a plurality of buffer descriptors in a first contiguous storage location segment of said host memory, each buffer descriptor containing physical address information and physical offset information identifying the location of one of said named data buffers in said host memory; storing a plurality of buffer descriptor pointers in a second contiguous storage location segment of said host memory, each buffer descriptor pointer containing a first starting address of said first contiguous storage location segment; storing a second starting address of said second contiguous storage location segment in a third contiguous storage location segment of said host memory; determining the location of a selected buffer descriptor pointer in response to said second starting address and a first index, said first index contained within said message and identifying said selected buffer descriptor pointer stored in said second contiguous storage location segment; determining the location of a selected buffer descriptor in response to said first starting address and a second index, said second index contained within said message and identifying said selected buffer descriptor stored in said first contiguous storage location segment; and. determining the location of said data in a selected one of said named data buffers in response to said physical address information and said physical offset information contained in said selected buffer descriptor, such that said port adapter accesses said data from non-contiguous addressable storage locations of said named data buffer in said host memory.
Claim 14
Dependent Claim 332 words
In a data processing system including an external node coupled to a host computer including a central processing unit (CPU), a host memory and an I/O port adapter, a mapping method for apportioning said host memory into a plurality of port pages for use by said port adapter when accessing data stored in named data buffers in said host memory in response to a message received from one of said CPU and said external node, said named data buffers generally comprising addressable storage locations in said host memory, said mapping method comprising the steps of: storing a plurality of buffer descriptors in a first contiguous storage location segment of said host memory, each buffer descriptor containing physical address information and physical offset information identifying the location of one of said named data buffers in said host memory; storing a plurality of buffer descriptor pointers in a second contiguous storage location segment of said host memory, each buffer descriptor pointer containing a first starting address of said first contiguous storage location segment; storing a second starting address of said second contiguous storage location segment in a third contiguous storage location segment of said host memory; determining the location of a selected buffer descriptor pointer in response to said second starting address and a first index, said first index contained within said message and identifying said selected buffer descriptor pointer stored in said second contiguous storage location segment; determining the location of a selected buffer descriptor in response to said first starting address and a second index, said second index contained within said message and identifying said selected buffer descriptor stored in said first contiguous storage location segment; and. determining the location of said data in a selected one of said named data buffers in response to said physical address information and said physical offset information contained in said selected buffer descriptor, such that said port adapter accesses said data from non-contiguous addressable storage locations of said named data buffer in said host memory.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-01-30 1998-08-01 1999-01-31 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-01-30 2002-08-01 2003-01-31 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-01-30 2006-08-01 2007-01-31 $7700.00 Window Closed / Lapsed

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