Memory management unit

Claim 2

A multiprocessor system having a first CPU and a second CPU, comprising: a first memory management unit coupled to said first CPU and including first buffer means having an address translation table storing memory control information to be used for converting a first logical address supplied from said first CPU to a first physical address based son said stored memory control information; a second memory management unit coupled to said second CPU and including second buffer means having an address translation table storing memory control information to be used for converting a second logical address supplied from said second CPU to a second physical address based on said stored memory control information; a common memory coupled to said first memory management unit and said second memory management unit through data transmission means and address transmission means; and a communication line coupled between said first memory management unit and said second memory management unit; each of said first and second memory management units having communication means for transmitting in series through said communication line multi-bit information relating to a change in said memory control information and for receiving multi-bit information relating to a change in memory control information from said communication line in series, and means for modifying the contents of the address translation table therein on the basis of the received multi-bit information, respectively.

Claim 3

A multiprocessor system according to claim 1, wherein said communication means in each of said first and second memory management units includes means for transmitting and receiving communication data in the form of a message containing identification information for designating one or a plurality of memory management units, a command portion and a data portion.

Claim 4

A multiprocessor system according to claim 2, wherein each of said first and second memory management units further includes calculation means for generating said communication data, and control means for controlling said calculation means and said communication means.

Claim 5

A multiprocessor system according to claim 1, wherein communication means in each of said first and second memory management units includes means for generating a message packet including said memory control information and transmitting means for transmitting a message packet on and for receiving a message packet from said communication line.

Claim 6

A multiprocessor system according to claim 4, wherein said transmitting means includes communication control means for controlling transmission and reception of packets message in accordance with a predetermined communication protocol.

Claim 7

A multiprocessor system according to claim 5, wherein said predetermined communication protocol gives priority to reception of message packets over transmission thereof on said communication line.

Claim 8

A multiprocessor system according to claim 1, wherein at least said first CPU and said first memory management unit are formed as a single chip microprocessor.

Claim 11

A method according to claim 8, wherein said step (b) comprises: (b1) generating in said first memory management unit a message including identification information which identifies said second memory management unit and said command; and (b2) transmitting said message from said first memory management unit to said second memory management unit via said communication line.

Claim 12

A method according to claim 9, wherein said step (b2) is controlled in accordance with a predetermined communication protocol.

Claim 13

A method according to claim 9, wherein said step (b2) is controlled in accordance with a communication protocol which given priority to receipt of messages over transmission thereof.

Claim 14

A multiprocessor system having a first CPU, a second CPU and a third CPU, comprising: a first memory management unit coupled to said first CPU and including means for converting a logical address supplied from said first CPU to a physical address based on stored memory control information; a second memory management unit coupled to said second CPU and including means for converting a logical address supplied from said second CPU to a physical address based on stored memory control information; a third memory management unit coupled to said third CPU and including means for converting a logical address supplied from said third CPU to a physical address based on stored memory control information; a common memory coupled to said first, second and third memory management units through data transmission means and address transmission means; a local memory coupled to at least two memory management units of said first, second and third memory management units through data transmission means and address transmission means; and a communication line coupled among said first, second and third memory management units; each of said first, second and third memory management units including means for providing a message, which has identification information for designating at least one of said first, second and third memory management units and multi-bit information relating to a change in said memory control information used for converting a logical address to physical address on said communication line as series data, means for receiving a message from said communication line as series data, means coupled to the receiving means for identifying the designated memory management unit on the basis of the identification information int he received message, and means coupled to the receiving means for modifying contents of the converting means on basis of the multi-bit information in the received message in the designated memory management unit.

Claim 15

A multiprocessor system having a first CPU, a second CPU and a third CPU, comprising: a first memory management unit coupled to said first CPU and including means for converting a logical address supplied from said first CPU to a physical address based on stored memory control information; a second memory management unit coupled to said second CPU and including means for converting a logical address supplied from said second CPU to a physical address based on stored memory control information; a third memory management unit coupled to said third CPU and including means for converting a logical address supplied from said third CPU to a physical address based on stored memory control information; a common memory coupled to said first, second and third memory management units through data transmission means and address transmission means; a local memory coupled to at least two memory management units of said first, second and third memory management units through data transmission means and address transmission means; and a communication line coupled among said first, second and third memory management units; each of said first, second and third memory management units including means for providing a message, which has identification information for designating at least one of said first, second and third memory management units and multi-bit information relating to a change in said memory control information used for converting a logical address to physical address on said communication line as series data, means for receiving a message from said communication line as series data, means coupled to the receiving means for identifying the designated memory management unit on the basis of the identification information int he received message, and means coupled to the receiving means for modifying contents of the converting means on basis of the multi-bit information in the received message in the designated memory management unit.

Claim 16

A multiprocessor system according to claim 12, wherein said communication line is coupled between said first and third memory management units via said second memory management unit.

Claim 17

A multiprocessor system according to claim 12, wherein each of said first, second and third memory management units is coupled to said communication line in parallel.

Claim 18

A multiprocessor system having a first CPU, a second CPU and a third CPU, comprising: a first memory management unit coupled to said first CPU and including buffer means having an address translation table for storing memory control information to be used for converting a logical address supplied from said first CPU to a physical address; a second memory management unit coupled to said second CPU and including buffer means having an address translation table for storing memory control information to be used for converting a logical address supplied from said second CPU to a physical address; a third memory management unit coupled to said third CPU and including buffer means having an address translation table for storing memory control information to be used for converting a logical address supplied from said third CPU to a physical address; a common memory coupled to said first, second and third memory management units through data transmission means and address transmission means; a local memory coupled to at least two memory management units of said first, second and third memory management units through data transmissions means and address transmission means; and a communication line coupled among said first, second and third memory management units; and each of said first, second and third memory management units including means for providing a message, which has identification information for designating at least one of said first, second and third memory management units and multi-bit information relating to a change in said memory control information used for converting a logical address to physical address on said communication line as series data, means for receiving a message from said communication line as series data, means coupled to receiving means for identifying the designated memory management unit on the basis of the identification information in the received message, and means coupled to the receiving message for modifying contents of the address translation table on the basis of the multi-bit information in the received message in the designated memory management unit.

Claim 19

A multiprocessor system having a first CPU, a second CPU and a third CPU, comprising: a first memory management unit coupled to said first CPU and including buffer means having an address translation table for storing memory control information to be used for converting a logical address supplied from said first CPU to a physical address; a second memory management unit coupled to said second CPU and including buffer means having an address translation table for storing memory control information to be used for converting a logical address supplied from said second CPU to a physical address; a third memory management unit coupled to said third CPU and including buffer means having an address translation table for storing memory control information to be used for converting a logical address supplied from said third CPU to a physical address; a common memory coupled to said first, second and third memory management units through data transmission means and address transmission means; a local memory coupled to at least two memory management units of said first, second and third memory management units through data transmissions means and address transmission means; and a communication line coupled among said first, second and third memory management units; and each of said first, second and third memory management units including means for providing a message, which has identification information for designating at least one of said first, second and third memory management units and multi-bit information relating to a change in said memory control information used for converting a logical address to physical address on said communication line as series data, means for receiving a message from said communication line as series data, means coupled to receiving means for identifying the designated memory management unit on the basis of the identification information in the received message, and means coupled to the receiving message for modifying contents of the address translation table on the basis of the multi-bit information in the received message in the designated memory management unit.

Claim 20

A multiprocessor system according to claim 15, wherein said communication line is coupled between said first and second memory management units via said second memory management unit.

Claim 21

A multiprocessor system according to claim 15, wherein each of said first, second and third memory management units is coupled to said communication line in parallel.

Claim 22

A multiprocessor system having a first CPU, a second CPU and a third CPU, comprising: a first memory management unit coupled to said first CPU and including means for converting a logical address supplied from said first CPU to a physical address based on stored memory control information; a second memory management unit coupled to said second CPU and including means for converting a logical address supplied from said second CPU to a physical address based on stored memory control information; a third memory management unit coupled to said third CPU and including means for converting a logical address supplied from said third CPU to a physical address based on stored memory control information; a common memory coupled to said first, second and third memory management units through data transmission means and address transmission means; a local memory coupled to said at least two memory management units of said first, second and third memory management units through data transmission means and address transmission means; and a communication line coupled among said first, second and third memory management units; each of said first, second and third memory management units including means for providing a message, which has identification information for designating at least one of said first, second and third memory management units and multi-bit information relating to a change in said memory control information used for converting a logical address to physical address, on said communication line as series data, means for receiving a message from said communication line as series data, and means coupled to the receiving means for identifying the designated memory management unit on the basis of the identification information in the received message information.

Claim 23

A multiprocessor system having a first CPU, a second CPU and a third CPU, comprising: a first memory management unit coupled to said first CPU and including means for converting a logical address supplied from said first CPU to a physical address based on stored memory control information; a second memory management unit coupled to said second CPU and including means for converting a logical address supplied from said second CPU to a physical address based on stored memory control information; a third memory management unit coupled to said third CPU and including means for converting a logical address supplied from said third CPU to a physical address based on stored memory control information; a common memory coupled to said first, second and third memory management units through data transmission means and address transmission means; a local memory coupled to said at least two memory management units of said first, second and third memory management units through data transmission means and address transmission means; and a communication line coupled among said first, second and third memory management units; each of said first, second and third memory management units including means for providing a message, which has identification information for designating at least one of said first, second and third memory management units and multi-bit information relating to a change in said memory control information used for converting a logical address to physical address, on said communication line as series data, means for receiving a message from said communication line as series data, and means coupled to the receiving means for identifying the designated memory management unit on the basis of the identification information in the received message information.

Claim 24

A multiprocessor system according to claim 18, wherein said communication line is coupled between said first and third memory management units via said second memory management unit.

Claim 25

A multiprocessor system according to claim 18, wherein each of said first, second and third memory management units is coupled to said communication line in parallel.