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US4897786A
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Bus window interlock
Assignee: Hewlett Packard Development Co LP
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Filing: 1987-09-04
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Granted: 1990-01-30
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Expires: 2007-09-04
Abstract
Abstract A system for implementing a bus window interlock scheme between a first and a second bus utilizes two bus window modules. The first bus window module coupled to the processor bus includes an interlock state bit which is set upon the acceptance of an interlock transaction from a processor. No further interlock transactions will be accepted while the interlock state bit is set. The interlock transaction is passed to a transaction buffer in the second bus window module which is coupled to memory through the memory bus. The transaction buffer passes the interlock data for memory to the memory bus while simultaneously loading a one deep interlock buffer. A confirmation is sent from the memory back to the transaction buffer. If the confirmation is interlock busy, then the interlock transaction is retried from the interlock buffer thus allowing the transaction buffer to process other commands. The interlock buffer waits for an unlock write signal before retrying an interlock transaction thus alleviating congestion on the memory bus.
Inventors
- 👤 David W. Pimm
- 👤 Paul J. Natusch
- 👤 Robert T. Silver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:48
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1657; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/4031; G06F13/4036
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
138 words
A system for implementing an interlocking scheme between a plurality of processors and a memory controller coupled to a first bus and a second bus respectively, comprising: (a) a first bus window module coupled to said first bus, said first bus window module receiving interlock transactions from said plurality of processors through said first bus; (b) a second bus window module coupled to said second bus and further coupled to said first bus window module, said second bus window module receiving one of said interlock transactions from said first bus window module and passing said one of said interlock transactions to said second bus, and wherein said first and second bus window modules further include a deadlock prevention circuit operating in said first and second bus window modules to prevent a system deadlock when transferring said interlock transactions.
Claim 2
Independent Claim
138 words
A system for implementing an interlocking scheme between a plurality of processors and a memory controller coupled to a first bus and a second bus respectively, comprising: (a) a first bus window module coupled to said first bus, said first bus window module receiving interlock transactions from said plurality of processors through said first bus; (b) a second bus window module coupled to said second bus and further coupled to said first bus window module, said second bus window module receiving one of said interlock transactions from said first bus window module and passing said one of said interlock transactions to said second bus, and wherein said first and second bus window modules further include a deadlock prevention circuit operating in said first and second bus window modules to prevent a system deadlock when transferring said interlock transactions.
Claim 3
Dependent Claim
16 words
A system according to claim 1 wherein said interlock transactions are interlock reads and unlock writes.
Claim 4
Dependent Claim
89 words
A system according to claim 2 wherein said deadlock prevention circuit for transferring interlock transactions in said first bus window module comprises: (a) a state bit located in said first bus window module, said state bit being set when an interlock transactions is accepted from one of said plurality of processors through the first bus; and (b) a confirmation signal provided to one of said plurality of processors when an interlock transaction is generated by said one processor, said confirmation signal depending upon the setting of the state bit.
Claim 5
Dependent Claim
46 words
A system according to claim 3 wherein said confirmation signal is an interlock busy signal if the state bit is set, said interlock busy signal keeping the processors from passing interlock transactions to the first bus until an unlock write is detected on said first bus.
Claim 6
Dependent Claim
129 words
A system according to claim 3 wherein said deadlock prevention circuit for transferring interlock transactions in said second bus window module comprises: (a) an interlock buffer located in said second bus window module; (b) a transaction buffer located in said second bus window module for receiving the one interlock transaction from said first bus window module, said transaction buffer further passing the one interlock transaction to said memory controller through the second bus and simultaneously stroking the one interlock transaction in said interlock buffer for subsequent retransmission of said one interlock transaction to said memory controller; (c) a transaction confirmation signal provided to said transaction buffer when the one interlock transaction is passed to said memory controller, said transaction confirmation signal depending upon the state of the memory controller.
Claim 7
Dependent Claim
48 words
A system according to claim 5 wherein said transaction confirmation signal is an interlock busy if the memory controller is locked, said interlock busy signal keeping the interlock buffer pending until an unlock write is detected and then retransmitting said one interlock transaction stored in said interlock buffer.
Claim 8
Dependent Claim
25 words
A system according to claim 5 wherein said transaction confirmation signal is a busy signal thus making the transaction buffer retry the one interlock transaction.
Claim 9
Dependent Claim
29 words
A system according to claim 5, wherein said transaction confirmation signal is a noack if there is no response thus making the transaction buffer retry the one interlock transaction.
Claim 10
Dependent Claim
36 words
A system according to claim 5, wherein said transaction confirmation signal is an ack signal if the interlock transaction is accepted by said memory controller, said ack signal indicating a clear status of said interlock buffer.
Claim 11
Dependent Claim
15 words
A system according to claim 5 wherein said interlock buffer is a one deep buffer.
Claim 12
Dependent Claim
75 words
A system according to claim 5 wherein said system is performing a direct memory access operation, further comprising: (a) an I/O device coupled to said second bus; and (b) means for changing an unlock write signal from said I/O device to a write signal before passing said write signal through the first bus window module to said first bus, said write signal being used to invalidate data in a cache memory in said one processor.
Claim 13
Independent Claim
96 words
A method for implementing an interlocking scheme between a plurality of processors and a memory controller coupled to a first bus and a second bus, respectively, comprising the steps of: (a) generating interlock transactions from said processor and said memory controller; and (b) transferring one of said interlock transactions from one of said processors to said memory controller via a first bus window module and a second bus window module; and (c) operating a deadlock prevention circuit in said first and second bus window modules to prevent a system deadlock when transferring said one interlock transaction.
Claim 14
Independent Claim
96 words
A method for implementing an interlocking scheme between a plurality of processors and a memory controller coupled to a first bus and a second bus, respectively, comprising the steps of: (a) generating interlock transactions from said processor and said memory controller; and (b) transferring one of said interlock transactions from one of said processors to said memory controller via a first bus window module and a second bus window module; and (c) operating a deadlock prevention circuit in said first and second bus window modules to prevent a system deadlock when transferring said one interlock transaction.
Claim 15
Dependent Claim
20 words
A method according to claim 12 wherein said step of generating interlock transactions creates interlock read and unlock write commands.
Claim 16
Dependent Claim
199 words
A method according to claim 13 wherein said step of operating a deadlock prevention circuit, further comprises the steps of: (a) setting a state bit located in the first bus window module when said one interlock transaction is accepted from said one processor through the first bus; (b) generating an interlock busy signal whenever an interlock transaction is generated from a processor while said state bit is set; (c) not accepting said interlock transaction into said first bus window module when the interlock busy signal is generated; (d) resetting said state bit when an unlock write signal is accepted by said first bus window module; (e) passing said one accepted interlock transaction to a transaction buffer in the second bus window module; (f) storing said one accepted interlock transaction from said transaction buffer into an interlock buffer in said second bus window module; (g) attempting to simultaneously load said one accepted interlock transaction from said transaction buffer onto the second bus; (h) keeping said interlock buffer pending if said transaction buffer receives an interlock busy signal through said second bus; and (i) retrying a pending interlock buffer transaction after an unlock write signal is received on said second bus.
Claim 17
Dependent Claim
29 words
A method according to claim 14 wherein said step of storing said one accepted interlock transaction into the interlock buffer is carried out by using a one-deep interlock buffer.
Claim 18
Dependent Claim
29 words
A method according to claim 14 further comprising the step of retrying a transaction buffer interlock transaction if said transaction buffer receives a busy signal through said second bus.
Claim 19
Dependent Claim
29 words
A method according to claim 14 further comprising the step of retrying a transaction buffer interlock transaction if said transaction buffer receives a noack signal through said second bus.
Claim 20
Dependent Claim
29 words
A method according to claim 14 further comprising the step of indicating a clear status for the interlock buffer if an ack signal is received by said interlock buffer.
Claim 21
Dependent Claim
66 words
A method according to claim 14 for attempting a direct memory access operation, further comprising the steps of: (a) changing an unlock write signal generated by an I/O device on said second bus to a write signal in the second bus window module; and (b) passing said write signal through said first bus window module to invalidate data in a cache memory in said one processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-29 | 1993-07-31 | 1994-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-29 | 1997-07-31 | 1998-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-29 | 2001-07-31 | 2002-01-30 | $7700.00 | Window Closed / Lapsed |