Redundancy circuit having a spare memory block replacing defective memory cells in different blocks

Claim 1

A semiconductor memory device having a redundancy circuit for remedying defective columns having defective column addresses, said semiconductor memory device comprising: a plurality of blocks of memory cells, each of said blocks comprising a plurality of memory cells arranged in a matrix pattern having rows and columns, for storing binary data, each of said memory cells having an output; a plurality of bit lines respectively connected to the outputs of the memory cells, said bit lines being grouped into bit line pairs, each of said bit line pairs corresponding to one column, being used for transferring one binary data, and having a first address; a plurality of gate means, each for gating signals which are transmitted on bit lines of bit line pairs corresponding to at least two columns, each of said gate means having inputs to which the bit lines of said at least two columns are connected, a control input, and column outputs which are equal in number to the bit lines connected to the inputs; gate selection means for selecting one of the gate means by decoding a second address supplied thereto, said gate selection means having inputs for receiving said second address, and a plurality of control outputs respectively connected to each of the control inputs of the gate means; a plurality of blocks of spare memory cells, each block comprising a plurality of spare memory cells for storing binary data, each of said spare memory cells having an output; a plurality of spare bit lines respectively connected to each of the outputs of the spare memory cells, said spare bit lines being equal in number to bit lines which are gated by one of the gate means, said spare bit lines being grouped into spare bit line pairs, each of said bit line pairs corresponding to one column and being used for transferring one binary data; spare gate means for gating the outputs of the spare memory cells, said spare gate means having a control input, and column outputs which are equal in number to columns constituted by the spare bit lines, and inputs connected to the corresponding spare bit lines; a column selecting means for amplifying one column output signal selected in response to a third address, said column selecting means having inputs connected in parallel to the column outputs of the gate means and spare gate means, and inputs for receiving said third address; a defective-column decoder having a plurality of storage sections for storing defective-column addresses, inputs for receiving the second and third addresses used for selecting one bit line pair from among the bit line pairs, and an output from which a spare gate selection signal used for selecting the spare gate means is output when the second and third addresses received at the inputs coincide with the defective-column address, the Spare gate selection signal generating, in response to each of the defective-column addresses, one of the column outputs of the gate means which are output in response to the selection of said spare gate selection signal by said column selecting means; and means, having an input supplied with the spare gate selection signal, for prohibiting the control outputs of the gate selection means in response to the spare gate selection signal, wherein the control input of a single spare gate means is used to replace first and second defective memory cells included in first and second blocks which are located in different blocks.