Memory circuit capable of replacing a faulty column with a spare column

Claim 2

A memory circuit for connection to a data bus having a plurality of data bus lines corresponding respectively to a plurality of bit positions for the transmission of respective bits of a data word arranged between a most significant bit position and a least significant bit position, the circuit comprising: a memory array having a plurality of memory cells arranged in rows and columns; a plurality of column select circuits for enabling access to columns in said array, each column select circuit being associated with a respective one of a plurality of groups of said columns and being arranged to access a selected on of the columns in one of said plurality of respective groups; at least one spare memory column; access circuitry for accessing said at least one spare column; a plurality of read circuits associated respectively with said plurality of groups of columns, and with said at least one spare column, for reading data bits onto the data bus in respective ones of said bit positions from the columns selected by the column select circuits; routing circuitry comprising a plurality of sets of first and second gate elements, each set associated with one of said groups of columns, the first gate element of each set being connected between one of said read circuits, associated with a respective one of said plurality of groups of columns, and a respective one of said data bus lines normally associated with said respective one of said plurality of groups and the second gate element of each set being connected between one of said read circuits, associated with one of said groups of columns adjacent to said respective one of said plurality of groups of columns, and said respective one of said data bus lines of the data bus; a plurality of logic circuits associated respectively with said plurality of groups of columns, each logic circuit being connected to receive a column group signal, having a predetermined logic value depending on whether or not one of said groups of columns contains a faulty column, and a column signal having a predetermined logic value depending on whether or not said faulty column has been selected; said logic circuits being connected to supply to the first and second gate elements respective control signals of opposite logic values so that one of the first and second gate elements is conductive while the other of the gate element is non-conductive; said control signals being supplied so that, on an attempted access to said faulty column, the first gate element associated with said one of said groups of columns containing said faulty column is rendered non-conductive so as to disconnect the read circuit associated with said one of said groups of columns from the data bus; said second gate elements associated with one of said groups of columns containing said faulty column and all of the groups of columns to one side of the groups of columns containing said faulty column and including said at least one spare column are rendered conductive; and said first gate elements associated with groups of columns to the other side of said group of columns containing the faulty column are rendered conductive whereas on an access to a column other than said faulty column within the group of columns containing the faulty column, the read circuit associated with said one of said groups of columns remains connected to the data bus, whereby one faulty column may be replaced by a corresponding column from an adjacent group.

Claim 3

The memory circuit as claimed in claim 1, which further comprises column address decoding circuitry associated with the column select circuits for decoding column addresses.

Claim 4

The memory circuit as claimed in claim 1, wherein each read circuit comprises a sense amplifier.

Claim 5

The memory circuit as claimed in claim 1, in which each row of the memory array is arranged to store more than one data word, only one data bit of each data word being stored in any one group of columns, wherein the number of the columns in each group is equal to the number of data words to be stored in each row, and the number of groups of columns is equal to the number of data bits making up each data word with correspondingly positioned bits of each data word being stored in each group of columns.

Claim 6

The memory circuit as claimed in claim 1, in which said access circuitry comprises another column select circuit.

Claim 7

The memory circuit as claimed in claim 1, wherein, when access to said faulty column is attempted, said at least one spare column is connected either to one of said data bus lines corresponding to the most significant bit with adjacent groups being connected to adjacent lower bit positions or to one of said data bus lines corresponding to the least significant bit position with adjacent groups being connected to adjacent higher bit positions.

Claim 8

The memory circuit as claimed in claim 1, wherein the first and second gate elements are field effect transistors having their gate electrodes connected to receive the control signals from the logic circuits.

Claim 9

The memory circuit as claimed in claim 1, further comprising a faulty column select circuit which comprises a plurality of fuses which can selectively be blown to identify the position of the faulty column within the group to produce said column signal.

Claim 10

A memory circuit as claimed in claim 2, which further comprises a write driver for actuating each said write circuit and circuit for disabling said write driver of one of said write circuits which has been disconnected from the data bus.

Claim 11

A memory circuit as claimed in claim 1, in which each row of the memory array is arranged to store more than one data word, only one data bit of each data word being stored in any one group of columns, wherein the number of columns in each group is equal to the number of data words to be stored in each row, and the number of groups of columns is equal to the number of data bits making up each data word with correspondingly positioned bits of each data word being stored in each group of columns and in which said access circuitry comprises a column select circuit.

Claim 12

The memory circuit as claimed in claim 1 wherein each of said logic circuits comprises a NAND gate which has one input selectively connected to ground or to a supply voltage, depending on whether or not one of said groups of columns associated with said NAND gate contains a faulty column, and another input connected to receive said column signal.

Claim 13

The memory circuit as claimed in claim 11, further comprising a plurality of fuses connected respectively between said one input of each logic circuit and ground, the groups of columns containing the faulty column being identified by blowing the fuse associated with said group of columns containing said faulty column.

Claim 14

A memory circuit for connection to a data bus having a plurality of data bus lines corresponding respectively to a plurality of bit positions for the transmission of respective bits of a data word arranged between a most significant bit position and a least significant bit position, the circuit comprising: a memory array having a plurality of memory cells arranged in rows and columns; a plurality of column select circuits for enabling access to columns to said array, each column select circuit being associated with a respective one of a plurality of groups of said columns and being arranged to access a selected one of the columns in one of said plurality of respective groups; at least one spare memory column; access circuitry arranged to access said at least one spare column; a plurality of write circuits associated respectively with said plurality of groups of columns, and with said at least one spare column, for writing data bits from the data bus in respective ones of said bit positions to the columns selected by the column select circuits; routing circuitry comprising a plurality of sets of first and second gate elements, each set associated with one of said groups of columns, the first gate element of each set being connected between one of said write circuits, associated with a respective one of said plurality of groups of columns, and a respective one of said data bus lines normally associated with said respective one of said plurality of groups and the second gate element of each set being connected between one of said write circuits, associated with one of said groups of columns adjacent to said respective one of said plurality of groups of columns, and said respective one of said data bus lines of the data bus; a plurality of logic circuits associated respectively with said plurality of groups of columns, each logic circuit being connected to receive a column group signal, having a predetermined logic value depending on whether or not one of said groups of columns contains a faulty column, and a column signal having a predetermined logic value depending on whether or not said faulty column has been selected; said logic circuits being connected to supply to the first and second gate elements respective control signals of opposite logic values so that one of the first and second gate elements is conductive while the other of the gate elements is non-conductive; said control signals being supplied so that, on an attempted access to said faulty column, the first gate element associated with said one of said groups of columns containing said faulty column is rendered non-conductive so as to disconnect the write circuit associated with said one of said groups of columns from the data bus; said second gate elements associated with said one of said groups of columns containing said faulty column and all of the groups of columns to one side of the groups of columns containing said faulty column and including said at least one spare column are rendered conductive; and said first gate elements associated with groups of columns to the other side of said group of columns containing the faulty column are rendered conductive whereas on an access to a column other than said faulty column within the group of columns containing the faulty column, the write circuit associated with said one of said groups of columns remains connected to the data bus, whereby one faulty column may be replaced by a corresponding column from an adjacent group.

Claim 15

A memory circuit for connection to a data bus having a plurality of data bus lines corresponding respectively to a plurality of bit positions for the transmission of respective bits of a data word arranged between a most significant bit position and a least significant bit position, the circuit comprising: a memory array having a plurality of memory cells arranged in rows and columns; a plurality of column select circuits for enabling access to columns to said array, each column select circuit being associated with a respective one of a plurality of groups of said columns and being arranged to access a selected one of the columns in one of said plurality of respective groups; at least one spare memory column; access circuitry arranged to access said at least one spare column; a plurality of write circuits associated respectively with said plurality of groups of columns, and with said at least one spare column, for writing data bits from the data bus in respective ones of said bit positions to the columns selected by the column select circuits; routing circuitry comprising a plurality of sets of first and second gate elements, each set associated with one of said groups of columns, the first gate element of each set being connected between one of said write circuits, associated with a respective one of said plurality of groups of columns, and a respective one of said data bus lines normally associated with said respective one of said plurality of groups and the second gate element of each set being connected between one of said write circuits, associated with one of said groups of columns adjacent to said respective one of said plurality of groups of columns, and said respective one of said data bus lines of the data bus; a plurality of logic circuits associated respectively with said plurality of groups of columns, each logic circuit being connected to receive a column group signal, having a predetermined logic value depending on whether or not one of said groups of columns contains a faulty column, and a column signal having a predetermined logic value depending on whether or not said faulty column has been selected; said logic circuits being connected to supply to the first and second gate elements respective control signals of opposite logic values so that one of the first and second gate elements is conductive while the other of the gate elements is non-conductive; said control signals being supplied so that, on an attempted access to said faulty column, the first gate element associated with said one of said groups of columns containing said faulty column is rendered non-conductive so as to disconnect the write circuit associated with said one of said groups of columns from the data bus; said second gate elements associated with said one of said groups of columns containing said faulty column and all of the groups of columns to one side of the groups of columns containing said faulty column and including said at least one spare column are rendered conductive; and said first gate elements associated with groups of columns to the other side of said group of columns containing the faulty column are rendered conductive whereas on an access to a column other than said faulty column within the group of columns containing the faulty column, the write circuit associated with said one of said groups of columns remains connected to the data bus, whereby one faulty column may be replaced by a corresponding column from an adjacent group.

Claim 16

The memory circuit as claimed in claim 13, which further comprises column address decoding circuitry associated with the column select circuits for decoding column addresses.

Claim 17

The memory circuit as claimed in claim 13, wherein each said write circuit comprises a write driver.

Claim 18

The memory circuit as claimed in claim 13, in which each row of the memory array is arranged to store more than one data word, only one data bit of each data word being stored in any one group of columns, wherein the number of columns in each group is equal to the number of data words to be stored in each row, and the number of groups of columns is equal to the number of data bits making up each word with correspondingly positioned bits of each data word being stored in each group of columns.

Claim 19

The memory circuit as claimed in claim 13, in which said access circuitry comprises another column select circuit.

Claim 20

The memory circuit as claimed in claim 13 wherein on an attempted access to said faulty column said at least one spare column is connected either to one of said data bus lines corresponding to the most significant bit with adjacent groups being connected to adjacent lower bit positions or to one of said data bus lines corresponding to the least significant bit position with adjacent groups being connected to adjacent higher bit positions.

Claim 21

The memory circuit as claimed in claim 13, wherein the first and second gate elements are field effect transistors having their gate electrodes connected to receive the control signals from the logic circuits.

Claim 22

The memory circuit as claimed in claim 13, further comprising a faulty column select circuit which comprises a plurality of fuses which can selectively be blown to identify the position of the faulty column within the group to produce said column signal.

Claim 23

The memory circuit as claimed in claim 13 wherein each of said logic circuits comprises a NAND gate which has one input selectively connected to ground or to a supply voltage, depending on whether or not one of said groups of columns associated with said NAND gate contains a faulty column, and another input connected to receive said column signal.

Claim 24

The memory circuit as claimed in claim 21, further comprising a plurality of fuses connected respectively between said one input of each logic circuit and ground, the group containing the faulty column being identified by blowing the fuse associated with that column group.