Semiconductor memory device with memory cell arrays and a redundant memory cell array associated with a small number of write-in and sense amplifying circuits

Claim 1

A semiconductor memory device fabricated on a single semiconductor chip, comprising: (a) a plurality of major memory cell blocks each divided into a plurality of major memory cell sub-blocks, each of said major memory cell sub-blocks having a plurality of major memory cells arranged in rows and columns; (b) a redundant memory cell block having a plurality of redundant memory cells arranged in rows and columns, said redundant memory cells being equal in number to said major memory cells of each major memory cell sub-block; (c) a plurality of word lines each coupled to said major memory cells in each row of each major memory cell sub-block, each of said word lines being further coupled to said redundant memory cells in each row of said redundant memory cell block; (d) a row decoder circuit responsive to a row address signal and operative to activate one of said word lines; (e) a plurality of first bit line pairs each coupled to said major memory cells in each column of each major memory cell sub-block, data bits stored in said major memory cells respectively appearing on said first bit line pairs upon activation of said word line; (f) a plurality of second bit line pairs each coupled to said redundant memory cells in each column of said redundant memory cell block, data bits stored in said redundant memory cells respectively appearing on said second bit line pairs upon activation of said word line; (g) a first column decoder circuit responsive to a column address signal and producing a first control signal; (h) a plurality of first column selectors each provided in association with one of said major memory cell sub-blocks and said redundant memory cell block, each of said first column selectors being responsive to said first control signal and operative to select one data bit from said data bits appearing on said first bit line pairs for each major memory cell sub-block or appearing on said second bit line pairs for said redundant memory cell block; (i) a second column decoder circuit responsive to said column address signal and producing a second control signal and an information signal; (j) a plurality of second column selectors each provided in association with each of said major memory cell blocks, each responsive to said second control signal and operative to transmit one of data bits supplied from said first column selectors provided in association with each major memory cell sub-block; (k) a plurality of combined circuits for write-in and sense amplifying operations coupled to said second column selectors and said first selector provided in association with said redundant memory cell block, respectively; (l) a redundant information storage capable of storing memory locations of said major memory cells detected as defective major memory cells, said redundant information storage being responsive to said information signal and operative to produce a third control signal; and (m) a shifting circuit responsive to said third control signal and operative to replace the data bit supplied from one of said defective major memory cells with the data bit supplied from said redundant memory cell, respectively.