Abstract A redundancy circuit for a semiconductor memory device of the byte configuration type, in which data is read out for each bit, is comprised of a main memory having a plurality of main memory cells arrayed in a matrix fashion, the matrix array being divided into memory sections in the column direction; a spare memory for saving defective memory cells contained in the main memory, the spare memory comprising spare rows of a plurality of spare memory cells arranged in the row direction, the spare row being provided for each of the main memory sections; programmable spare row decoders provided for each row of spare memory cells and for independently selecting each row of the spare memory cell; and main-decoder-disable signal-generating circuits provided for each of the memory sections and for placing all of the row main decoders of the corresponding memory section in non-select state in response to a signal derived from the programmed spare row decoder of the corresponding memory section.
A semiconductor memory device, comprising: a main memory having a plurality of main memory cells arranged in a matrix array of rows and columns, said matrix array being divided in the column direction into a plurality of main memory sections; a plurality of spare memory means, each of said spare memory means individually corresponding to a respective one of said main memory sections, for replacing defective memory cells contained in said main memory sections, said spare memory means each comprising a plurality of spare memory cells arranged in rows; a plurality of programmable spare row decoder means for selecting said spare memory means, each of said spare row decoder means individually selecting a respective one of said rows of spare memory cells; and a plurality of means for disabling said main memory sections in response to a signal from said programmable spare row decoder means, each of said disabling means individually corresponding to one of said main memory sections.
Claim 2
Dependent Claim
159 words
A semiconductor memory device, comprising: a main memory having a plurality of main memory cells arranged in a matrix array of rows and columns, said matrix array being divided in the column direction into a plurality of main memory sections; a plurality of spare memory means, each of said spare memory means individually corresponding to a respective one of said main memory sections, for replacing defective memory cells contained in said main memory sections, said spare memory means each comprising a plurality of spare memory cells arranged in rows; a plurality of programmable spare row decoder means for selecting said spare memory means, each of said spare row decoder means individually selecting a respective one of said rows of spare memory cells; and a plurality of means for disabling said main memory sections in response to a signal from said programmable spare row decoder means, each of said disabling means individually corresponding to one of said main memory sections.
Claim 3
Dependent Claim
13 words
A semiconductor memory device according to claim 1, comprising two main memory sections.