Void free oxide fill for interconnect spaces

Claim 2

An improved process for void free oxide fill of spaces between metal in a patterned metal interconnect layer of an integrated circuit comprising: (a) depositing a first plasma enhanced oxide layer of approximately 2500 Å over said metal interconnect layer on said integrated circuit, said interconnect layer having spaces between metal strips, said first oxide layer being thin enough so that deposited oxide on the opposite side walls of said interconnect metal are not connected; (b) applying an approximately 150 Å thick layer of hardenable sacrificial SOG material over said first plasma enhanced oxide layer, said SOG material forming a partial plug in said space between said metal interconnects, the viscosity of said layer of hardenable sacrificial SOG material selected so that it will flow into said spaces between said metal strips; (c) simultaneously dry etching said oxide layer and said material plug until all of said SOG is removed and approximately 90% of said first plasma enhanced oxide layer has been removed; and (d) depositing a second layer of plasma enhanced oxide over said dry etched integrated circuit.

Claim 3

The process of claim 1 wherein said SOG material plug forms primarily by capillary action.

Claim 4

The process of claim 1 wherein the metal interconnect has a height (H) less than one micron and the width of some of the interconnect spaces (W) are equal to or greater than 0.55 microns and some of the interconnect spaces have an aspect ratio H/W greater than 1.0.

Claim 5

An improved method for depositing interlayer dielectric oxide to fill integrated circuit spaces between a patterned interconnect metal layer, the width of some of said spaces (W) being as narrow as 0.55 microns and having heights (H) on the order of 1.0 micron comprising: (a) depositing a first layer of oxide over said patterned interconnect metal layer, said first oxide layer thickness being about the height of said interconnect metal strips; (b) applying an approximately 150 Å thick layer of a hardenable SOG material having an etch rate greater than the etch rate of said oxide, said SOG material filling in the spaces between said interconnect metal strips; (c) hardening said SOG layer; (d) simultaneously backetching both said first layer of oxide and said hardened SOG material, until said hardened SOG material is entirely removed and approximately 90% of said first oxide layer is removed; (e) depositing a second coating of said oxide over said etched integrated circuit, said second coating being a oxide; (f) planarizing said second oxide coating; (g) applying resist to said integrated circuit; (h) patterning said resist for a third layer metallization; (i) depositing said third layer metallization; (j) repeating steps (a) through (e) over said third layer metallization.

Claim 6

An improved method for depositing interlayer dielectric oxide to fill integrated circuit spaces between a patterned interconnect metal layer, the width of some of said spaces (W) being as narrow as 0.55 microns and having heights (H) on the order of 1.0 micron comprising: (a) depositing a first layer of oxide over said patterned interconnect metal layer, said first oxide layer thickness being about the height of said interconnect metal strips; (b) applying an approximately 150 Å thick layer of a hardenable SOG material having an etch rate greater than the etch rate of said oxide, said SOG material filling in the spaces between said interconnect metal strips; (c) hardening said SOG layer; (d) simultaneously backetching both said first layer of oxide and said hardened SOG material, until said hardened SOG material is entirely removed and approximately 90% of said first oxide layer is removed; (e) depositing a second coating of said oxide over said etched integrated circuit, said second coating being a oxide; (f) planarizing said second oxide coating; (g) applying resist to said integrated circuit; (h) patterning said resist for a third layer metallization; (i) depositing said third layer metallization; (j) repeating steps (a) through (e) over said third layer metallization.

Claim 7

The method of claim 4 wherein the step of simultaneously backetching consists of a plasma dry etch.

Claim 8

The method of claim 5 wherein said dry etch employs CF4 and Argon gases.

Claim 9

In an improved process for void free oxide fill of spaces between metal in a metal interconnect layer of an integrated circuit where the height (H) of said metal in said interconnect layer and a portion of the width of spaces (W) between said metal have an aspect ratio HNV greater than 1.0, the improvement comprising: (a) depositing a first oxide layer over said metal interconnect layer on said integrated circuit, said first oxide layer being thin enough so that deposited oxide on the opposite side walls of said interconnect metal are not connected; (b) applying a layer of hardenable sacrificial SOG material over said first oxide layer, said SOG material forming a partial plug in said spaces between said metal interconnect, said layer of SOG material being approximately six percent as thick as the thickness of said first oxide layer; (c) simultaneously dry etching said oxide layer and said material plug until essentially all of the SOG is removed and approximately 90% of said oxide layer has been removed; and (d) depositing a second layer of oxide over said dry etched integrated circuit.

Claim 10

In an improved process for void free oxide fill of spaces between metal in a metal interconnect layer of an integrated circuit where the height (H) of said metal in said interconnect layer and a portion of the width of spaces (W) between said metal have an aspect ratio HNV greater than 1.0, the improvement comprising: (a) depositing a first oxide layer over said metal interconnect layer on said integrated circuit, said first oxide layer being thin enough so that deposited oxide on the opposite side walls of said interconnect metal are not connected; (b) applying a layer of hardenable sacrificial SOG material over said first oxide layer, said SOG material forming a partial plug in said spaces between said metal interconnect, said layer of SOG material being approximately six percent as thick as the thickness of said first oxide layer; (c) simultaneously dry etching said oxide layer and said material plug until essentially all of the SOG is removed and approximately 90% of said oxide layer has been removed; and (d) depositing a second layer of oxide over said dry etched integrated circuit.