Method for planarizing an integrated circuit structure

Abstract

Abstract A planarizing process as disclosed for planarizing an integrated circuit structure (10) using a low melting inorganic planarizing material (30) which comprises depositing a low melting inorganic planarizing layer (3) such as a boron oxide glass over a layer of insulating material (20) such as an oxide of silicon and then dry etching the low melting inorganic planarizing layer (3) to planarize the structure. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are carried out without removing the integrated circuit structure from the vacuum apparatus. An additional etching step may be carried out after depositing the insulating layer (20) to remove any voids formed in the insulating layer (20).

Inventors

• 👤 Jeffrey Marks
• 👤 Kam Shing Law
• 👤 David Nin-Kou Wang
• 👤 Dan Maydan

Bibliographic Details