Patent US5382533A successfully refreshed from Google Patents.
US5382533A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing small geometry MOS field-effect transistors having improved barrier layer to hot electron injection
Assignee: Micron Technology Inc
•
Filing: 1993-06-18
•
Granted: 1995-01-17
•
Expires: 2013-06-18
Abstract
Abstract A process for suppressing hot electrons in sub half micron MOS devices wherein a gate oxide and a gate electrode are formed on the surface of a silicon substrate and source and drain regions are ion implanted into the silicon substrate using the gate electrode as a mask. The process includes forming a layer of silicon dioxide over the gate electrode and over the source and drain regions of the substrate, and then introducing a barrier layer forming element into the layer of silicon dioxide to form a thin barrier region to hot electrons at the interface between the silicon substrate and the silicon dioxide. In a preferred embodiment of the invention, nitrogen is introduced into the silicon dioxide by heating the wafer in a rapid thermal processor and in the presence of a nitrogen containing gas at an elevated temperature for a predetermined time. The nitrogen containing gas may be selected from the group consisting of nitrogen trifluoride, ammonia and nitrous oxide. In an alternative embodiment of the invention, fluorine atoms are introduced into the silicon substrate either as the sole barrier layer forming element (silicon fluoride) or prior to the formation of the thin silicon nitride region. The fluorine atoms form good strong silicon-fluorine bonds in the silicon substrate and thereby further enhance the hot electron suppression. In a third embodiment, nitrogen and fluorine are reacted in a rapid thermal processor to form a composite barrier layer of Si 3 N 4 and SF.
Inventors
- 👤 Aftab Ahmad
- 👤 Randhir P. S. Thakur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:09
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/683; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01338; H10D64/693; Y; Y10; Y10S; Y10S438/00; Y10S438/91
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
153 words
A process for manufacturing an insulated-gate, field-effect transistor of the type having a gate oxide layer formed on a silicon substrate, a gate electrode formed on top of the gate oxide layer, and a channel region that was masked by the gate electrode during the implantation of ionic species into the transistor's source and drain regions, said process characterized by the following sequence of steps: (a) forming a silicon dioxide layer over said gate electrode and over said source and drain regions; and (b) introducing fluorine, or fluorine in combination with nitrogen into the surface of the silicon substrate, so as to form a barrier layer comprising either silicon fluoride or both silicon fluoride and silicon nitride components at an interface between the silicon dioxide layer and the silicon substrate, said fluorine being implanted in ionic form into the surface of the silicon substrate with implantation energies in the range of 15-30 Kev.
Claim 2
Dependent Claim
153 words
A process for manufacturing an insulated-gate, field-effect transistor of the type having a gate oxide layer formed on a silicon substrate, a gate electrode formed on top of the gate oxide layer, and a channel region that was masked by the gate electrode during the implantation of ionic species into the transistor's source and drain regions, said process characterized by the following sequence of steps: (a) forming a silicon dioxide layer over said gate electrode and over said source and drain regions; and (b) introducing fluorine, or fluorine in combination with nitrogen into the surface of the silicon substrate, so as to form a barrier layer comprising either silicon fluoride or both silicon fluoride and silicon nitride components at an interface between the silicon dioxide layer and the silicon substrate, said fluorine being implanted in ionic form into the surface of the silicon substrate with implantation energies in the range of 15-30 Kev.
Claim 3
Dependent Claim
45 words
The process of claim 1, wherein the fluorine which is incorporated in the barrier layer comprising both silicon fluoride and silicon nitride components is implanted in ionic form into the surface of the silicon substrate prior to the formation therein of the silicon nitride component.
Claim 4
Dependent Claim
61 words
The process of claim 1 wherein said silicon nitride component and said silicon fluoride component of the barrier layer having both silicon fluoride and silicon nitride components are formed separately by diffusion of one or more nitrogen-containing gases into the substrate during one rapid-thermal-processing step, and by diffusion of one or more fluorine-containing gases into the substrate during another rapid-thermal-processing step.
Claim 5
Dependent Claim
54 words
The process of claim 1 wherein said silicon nitride component and said silicon fluoride component of the barrier layer having both silicon nitride and silicon fluoride components are formed jointly and simultaneously by diffusion of one or more nitrogen-containing gases and one or more fluorine gases into the substrate during a single rapid-thermal-processing step.
Claim 6
Dependent Claim
117 words
A process for manufacturing a sub-half-micron, insulated-gate, field-effect transistor, wherein a gate oxide layer is formed on a silicon substrate, a gate electrode is formed on top of the gate oxide layer, and the gate electrode masks the transistor's channel region when ions are implanted into the substrate in the transistor's source and drain regions, said process characterized by the following sequence of steps: (a) forming a silicon dioxide layer over said gate electrode and over said source and drain regions; (b) implanting fluorine atoms into said silicon substrate; (c) introducing nitrogen into said silicon dioxide layer to form a thin layer of silicon nitride at the interface between said silicon dioxide layer and said silicon substrate.
Claim 7
Dependent Claim
117 words
A process for manufacturing a sub-half-micron, insulated-gate, field-effect transistor, wherein a gate oxide layer is formed on a silicon substrate, a gate electrode is formed on top of the gate oxide layer, and the gate electrode masks the transistor's channel region when ions are implanted into the substrate in the transistor's source and drain regions, said process characterized by the following sequence of steps: (a) forming a silicon dioxide layer over said gate electrode and over said source and drain regions; (b) implanting fluorine atoms into said silicon substrate; (c) introducing nitrogen into said silicon dioxide layer to form a thin layer of silicon nitride at the interface between said silicon dioxide layer and said silicon substrate.
Claim 8
Dependent Claim
186 words
A process for manufacturing an insulated-gate field-effect transistor, said process comprising the following sequence of steps: (a) forming a thin gate oxide layer on the surface of a silicon substrate; (b) forming a composite gate electrode on the surface of the gate oxide layer, said electrode having a lower layer of polycrystalline silicon and an upper layer of refractory metal silicide; (c) implanting ions into the transistor's source and drain regions, said ions being prevented from entering the transistor's channel region by said gate electrode which acts as an implant mask; (d) forming a silicon dioxide layer over said gate electrode and over said source and drain regions; (e) implanting fluorine ions into said silicon substrate; (f) introducing nitrogen into said silicon dioxide layer by heating said wafer to a temperature of at least 800° C. for at least 10 seconds in a rapid thermal processor in the presence of a nitrogen-containing gas selected from the group consisting of nitrogen trifluoride, ammonia, and nitrous oxide, and thus forming a thin layer of silicon nitride at the interface between said silicon dioxide layer and said silicon substrate.
Claim 9
Dependent Claim
186 words
A process for manufacturing an insulated-gate field-effect transistor, said process comprising the following sequence of steps: (a) forming a thin gate oxide layer on the surface of a silicon substrate; (b) forming a composite gate electrode on the surface of the gate oxide layer, said electrode having a lower layer of polycrystalline silicon and an upper layer of refractory metal silicide; (c) implanting ions into the transistor's source and drain regions, said ions being prevented from entering the transistor's channel region by said gate electrode which acts as an implant mask; (d) forming a silicon dioxide layer over said gate electrode and over said source and drain regions; (e) implanting fluorine ions into said silicon substrate; (f) introducing nitrogen into said silicon dioxide layer by heating said wafer to a temperature of at least 800° C. for at least 10 seconds in a rapid thermal processor in the presence of a nitrogen-containing gas selected from the group consisting of nitrogen trifluoride, ammonia, and nitrous oxide, and thus forming a thin layer of silicon nitride at the interface between said silicon dioxide layer and said silicon substrate.
References Cited (Backward Citations)
US4113515A
Cited
US5098866A
Cited
US5264380A
Cited
US5032545A
Cited
US5237188A
Cited
US5258333A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-16 | 1998-07-18 | 1999-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-16 | 2002-07-18 | 2003-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-16 | 2006-07-18 | 2007-01-17 | $7700.00 | Window Closed / Lapsed |