US5379434A
Expired / Lapsed
US
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Apparatus and method for managing interrupts in a multiprocessor system
Assignee: International Business Machines Corp
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Filing: 1994-06-10
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Granted: 1995-01-03
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Expires: 2014-06-10
Abstract
Abstract A system and method for selecting a processor to service interrupts in a multiprocessor system with processor individualized interrupt priority states. The interrupt priority information associated with the various processors is bit serially compared to select one or more processors of lowest interrupt priority status, Processor individualized identification information is then compared to reconcile when multiple processors have an identical interrupt priority level, The outcome is stored and immediately available for managing interrupts generated by I/O devices, In a preferred arrangement, the interrupt priority status of the selected processor is confirmed immediately before processing the service requests to compensate for any changes occurring during the period of the bit serial comparison.
Inventors
- 👤 Michael T. DiBrino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:06
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
80 words
Apparatus to select a processor for servicing interrupts in a system having a plurality of processors with individual interrupt priority information, comprising: means for bit serially comparing interrupt priority information among the processors, the comparison being done in repeated succession using bits of corresponding significance, connected to the plurality of processors; and means for selecting a processor of the plurality of processors to service an interrupt using priority results obtained from the comparison by the means for bit serially comparing.
Claim 2
Dependent Claim
80 words
Apparatus to select a processor for servicing interrupts in a system having a plurality of processors with individual interrupt priority information, comprising: means for bit serially comparing interrupt priority information among the processors, the comparison being done in repeated succession using bits of corresponding significance, connected to the plurality of processors; and means for selecting a processor of the plurality of processors to service an interrupt using priority results obtained from the comparison by the means for bit serially comparing.
Claim 3
Dependent Claim
19 words
The apparatus recited in claim 1, further comprising: means for using processor individualized identification information to select a processor.
Claim 4
Dependent Claim
17 words
The apparatus recited in claim 2, wherein the processor individualized identification information corresponds to processor serial numbers.
Claim 5
Dependent Claim
36 words
The apparatus recited in claim 3, further comprising: means for confirming the selection of a processor by comparing priority results from the means for bit serial comparison to the interrupt priority information of a selected processor.
Claim 6
Dependent Claim
24 words
The apparatus recited in claim 4, wherein the means for bit serially comparing identifies one or more processors as having the lowest interrupt priority.
Claim 7
Independent Claim
75 words
A method of selecting a processor for servicing interrupts in a system having a plurality of processors with individualized interrupt priority information, comprising the steps of: bit serially comparing interrupt priority information among the processors, the comparison being done in repeated succession using bits of corresponding significance, connected to the plurality of processors; and selecting a processor of the plurality of processors to service an interrupt using priority results obtained from the bit serial comparison.
Claim 8
Independent Claim
75 words
A method of selecting a processor for servicing interrupts in a system having a plurality of processors with individualized interrupt priority information, comprising the steps of: bit serially comparing interrupt priority information among the processors, the comparison being done in repeated succession using bits of corresponding significance, connected to the plurality of processors; and selecting a processor of the plurality of processors to service an interrupt using priority results obtained from the bit serial comparison.
Claim 9
Dependent Claim
20 words
The method recited in claim 6, comprising the further step of: using processor individualized identification information to select a processor.
Claim 10
Dependent Claim
22 words
The method recited in claim 7, wherein the processor individualized identification information is used to make a selection by processor serial number.
Claim 11
Dependent Claim
36 words
The method recited in claim 8, further comprising the step of: confirming the selection of a processor by comparing priority results from the bit serially comparing step to the interrupt priority information of a selected processor.
Claim 12
Dependent Claim
24 words
The method recited in claim 9, wherein the step of bit serially comparing identifies one or more processors as having the lowest interrupt priority.
Claim 13
Independent Claim
88 words
A system with resources for servicing interrupts based upon a comparison of processor interrupt priority information, comprising: a plurality of processors connected to service interrupts; means for bit serially comparing interrupt priority information among the processors, the comparison being done in repeated succession using bits of corresponding significance, connected to the plurality of processors; means for receiving an interrupt; and means for selecting a processor of the plurality of processors to service the interrupt using priority results obtained from the comparison by the means for bit serially comparing.
Claim 14
Independent Claim
88 words
A system with resources for servicing interrupts based upon a comparison of processor interrupt priority information, comprising: a plurality of processors connected to service interrupts; means for bit serially comparing interrupt priority information among the processors, the comparison being done in repeated succession using bits of corresponding significance, connected to the plurality of processors; means for receiving an interrupt; and means for selecting a processor of the plurality of processors to service the interrupt using priority results obtained from the comparison by the means for bit serially comparing.
Claim 15
Dependent Claim
21 words
The system recited in claim 11, further comprising: means for using processor individualized identification information to assist in selecting a processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-02 | 1998-07-04 | 1999-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-02 | 2002-07-04 | 2003-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-02 | 2006-07-04 | 2007-01-03 | $7700.00 | Window Closed / Lapsed |