US3660823A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Serial bit comparator with selectable bases of comparison
Assignee: Honeywell Inc
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Filing: 1970-07-20
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Granted: 1972-05-02
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Expires: 1990-07-20
Abstract
Abstract A serial by bit comparator device is disclosed for determining the relative magnitude of two binary numbers. The comparator comprises a plurality of storage means for storing interrogating bits therein. Each storage means represents a proposition relative to the numbers to be compared, and the presence of an interrogating bit in a storage means signifies that the proposition for which that storage means represents is true. The binary numbers to be compared are fed into the comparator, and depending on their relative magnitude, permit or inhibit the continued storage of the interrogating bit. Means are provided to sense in which of the storage means there still remains an interrogating bit, hence determining which proposition is true, or if a given proposition is true.
Inventors
- 👤 John A Recks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 06:53
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/02; G06F7/026; G06F7/22
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
195 words
A comparator device for comparing two binary numbers A and B, each number coded into a series of electrical signals sequentially arranged in decreasing order of significance, said comparator comprising: a. a plurality of storage elements each representing a proposition relative to the binary numbers to be compared; b. first means for introducing into each of said storage elements a first electronic signal representing an interrogating bit for storage in said storage elements, the presence of the first electric signal in any of said storage elements signifying an assertion of the truth of the proposition represented by said storage element; c. second means coupled to storage elements for introducing in selected ones of said storage elements the coded electric signals representing the binary numbers to be compared; d. said storage elements including third means responsive to the first electric signal representing the interrogating bit stored in said storage elements and to the coded electric signals representing the binary numbers to be compared, for adjusting the state of said storage elements; e. and fourth means responsive to the state of said storage elements for detecting the first electric signal in any one of said storage elements.
Claim 2
Dependent Claim
195 words
A comparator device for comparing two binary numbers A and B, each number coded into a series of electrical signals sequentially arranged in decreasing order of significance, said comparator comprising: a. a plurality of storage elements each representing a proposition relative to the binary numbers to be compared; b. first means for introducing into each of said storage elements a first electronic signal representing an interrogating bit for storage in said storage elements, the presence of the first electric signal in any of said storage elements signifying an assertion of the truth of the proposition represented by said storage element; c. second means coupled to storage elements for introducing in selected ones of said storage elements the coded electric signals representing the binary numbers to be compared; d. said storage elements including third means responsive to the first electric signal representing the interrogating bit stored in said storage elements and to the coded electric signals representing the binary numbers to be compared, for adjusting the state of said storage elements; e. and fourth means responsive to the state of said storage elements for detecting the first electric signal in any one of said storage elements.
Claim 3
Dependent Claim
72 words
A comparator device as recited in claim 1 wherein there are three storage elements, one storage element representing the proposition A is greater than B when having a ''''1'''' bit stored therein, another storage element representing the proposition that A is less than B when having a ''''1'''' bit stored therein, and still another storage element representing the proposition that A is equal to B when having a ''''1'''' bit stored therein.
Claim 4
Dependent Claim
58 words
A comparator device as recited in claim 2 wherein 8 combinations of interrogations are possible the ''''1'''' bit representing a possible query according to the following table: Hi Lo Equal 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 (Always compare) 0 0 0 (Never compare).
Claim 5
Dependent Claim
153 words
A bit serial comparator device for bit serially comparing and determining the relative magnitude of two binary numbers comprising: a. first recirculating amplifier circuit means settable for determining that a first binary digit is greater than a second binary digit; b. second recirculating amplifier circuit means coupled to said first means said second means settable for determining that a first binary digit is less than a second binary digit; c. third recirculating amplifier circuit means coupled to said first and second means said third means settable for determining that a first binary digit is equal to a second binary digit; d. input means coupled to said first, second and third means for introducing the first and second binary digits to each of said first, second and third means; e. and output means coupled to said first, second and third means for receiving and outputting an Answer from said first, second and third means.
Claim 6
Dependent Claim
153 words
A bit serial comparator device for bit serially comparing and determining the relative magnitude of two binary numbers comprising: a. first recirculating amplifier circuit means settable for determining that a first binary digit is greater than a second binary digit; b. second recirculating amplifier circuit means coupled to said first means said second means settable for determining that a first binary digit is less than a second binary digit; c. third recirculating amplifier circuit means coupled to said first and second means said third means settable for determining that a first binary digit is equal to a second binary digit; d. input means coupled to said first, second and third means for introducing the first and second binary digits to each of said first, second and third means; e. and output means coupled to said first, second and third means for receiving and outputting an Answer from said first, second and third means.
Claim 7
Dependent Claim
23 words
A serial comparator as recited in claim 4 including initializing means coupled to said first, second and third means for initializing said comparator.
Claim 8
Dependent Claim
26 words
A serial comparator as recited in claim 4 wherein said output means includes delay means for permitting changes in signal levels to propagate through said comparator.
Claim 9
Dependent Claim
161 words
In combination with a data processing system, a bit serial comparator device for bit serially comparing and determining the relative magnitude of two binary numbers comprising: a. first recirculating amplifier circuit means settable for determining that a first binary digit is greater than a second binary digit; b. second recirculating amplifier circuit means coupled to said first means said second means settable for determining that a first binary digit is less than a second binary digit; c. third recirculating amplifier circuit means coupled to said first and second means said third means settable for determining that a first binary digit is equal to a second binary digit; d. input means coupled to said first, second and third means said input means for introducing the first and second binary digits to each of said first, second and third means; e. and output means coupled to said first, second and third means for outputting an answer from said first, second and third means.
Claim 10
Dependent Claim
161 words
In combination with a data processing system, a bit serial comparator device for bit serially comparing and determining the relative magnitude of two binary numbers comprising: a. first recirculating amplifier circuit means settable for determining that a first binary digit is greater than a second binary digit; b. second recirculating amplifier circuit means coupled to said first means said second means settable for determining that a first binary digit is less than a second binary digit; c. third recirculating amplifier circuit means coupled to said first and second means said third means settable for determining that a first binary digit is equal to a second binary digit; d. input means coupled to said first, second and third means said input means for introducing the first and second binary digits to each of said first, second and third means; e. and output means coupled to said first, second and third means for outputting an answer from said first, second and third means.
Claim 11
Independent Claim
122 words
A method of serially comparing two binary numbers A and B to determine whether or not A is greater than, less than or equal to B, comprising: a. coding the binary members into a series of electrical signals sequentially arranged in decreasing order of significance; b. translating into electrical signals the propositions A is greater than B, A is less than B, and A is equal to B; c. comparing the electrically coded numbers, most significant digit first, with said electrically translated propositions; d. determining which proposition is valid in relation to the binary numbers A and B; e. eliminating the propositions determined not to apply to the numbers A and B; and f. strobing the valid propositions to the computer system.
Claim 12
Independent Claim
122 words
A method of serially comparing two binary numbers A and B to determine whether or not A is greater than, less than or equal to B, comprising: a. coding the binary members into a series of electrical signals sequentially arranged in decreasing order of significance; b. translating into electrical signals the propositions A is greater than B, A is less than B, and A is equal to B; c. comparing the electrically coded numbers, most significant digit first, with said electrically translated propositions; d. determining which proposition is valid in relation to the binary numbers A and B; e. eliminating the propositions determined not to apply to the numbers A and B; and f. strobing the valid propositions to the computer system.
References Cited (Backward Citations)
US2889534A
Cited
US3218609A
Cited
US3237159A
Cited
US3241114A
Cited
US3434109A
Cited
US3479644A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-02 | 1975-11-01 | 1976-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-02 | 1979-11-01 | 1980-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-02 | 1983-11-01 | 1984-05-02 | $7700.00 | Window Closed / Lapsed |