Abstract A process for directing an interrupt request from an interrupting device to a selected number of processing devices by a bus. The interrupting device asserts one or more data lines during an interrupt command, each asserted data line corresponding to a selected processing device to which the interrupt command is directed. During an identify transaction, the interrupting device monitors which data line is asserted by a processing device to determine whether the asserted data line corresponds to a processing device selected by a destination mask stored in the interrupting device. Subsequently, one or more data lines are asserted by the interrupting device corresponding to a particular interrupt routine. The interrupting device itself selects particular processing devices, eliminating the need for a central interrupt arbiter. The process allows the interrupting device to seek interrupt servicing from any number of other devices, and to accept service from the first device which is available.
A process for directing an interrupt request from an interrupting device to a selected number of processing devices connected to the interrupting device by a bus, the bus including a plurality of information lines for transferring a plurality of commands, and a plurality of data lines for transferring data, the steps performed by the interrupting device comprising: asserting during an interrupt command a selected number of data lines, each asserted data line corresponding to a selected processing device to which the interrupt command is directed, and the asserted data lines corresponding to a destination mask stored in an interrupt destination register means in the interrupting device; asserting during an interrupt command a data line, the asserted data line corresponding to a priority level of the interrupt command, and the asserted data line corresponding to an interrupt level stored in an interrupt control register means in the interrupting device; monitoring which data line is asserted by a processing device during one cycle of an identify transaction to determine whether the asserted data line corresponds to the interrupt level stored in the interrupt control register means; monitoring which data line is asserted by a processing device during another cycle of the identify transaction to determine whether the asserted data line corresponds to a processing device selected by the destination mask stored in the interrupt destination register means; and asserting during a subsequent cycle of the identify transaction a data line, the asserted data line corresponding to a particular interrupt routine, and the asserted data line corresponding to an interrupt vector stored in a vector register means in the interrupting device.
Claim 2
Dependent Claim
268 words
A process for directing an interrupt request from an interrupting device to a selected number of processing devices connected to the interrupting device by a bus, the bus including a plurality of information lines for transferring a plurality of commands, and a plurality of data lines for transferring data, the steps performed by the interrupting device comprising: asserting during an interrupt command a selected number of data lines, each asserted data line corresponding to a selected processing device to which the interrupt command is directed, and the asserted data lines corresponding to a destination mask stored in an interrupt destination register means in the interrupting device; asserting during an interrupt command a data line, the asserted data line corresponding to a priority level of the interrupt command, and the asserted data line corresponding to an interrupt level stored in an interrupt control register means in the interrupting device; monitoring which data line is asserted by a processing device during one cycle of an identify transaction to determine whether the asserted data line corresponds to the interrupt level stored in the interrupt control register means; monitoring which data line is asserted by a processing device during another cycle of the identify transaction to determine whether the asserted data line corresponds to a processing device selected by the destination mask stored in the interrupt destination register means; and asserting during a subsequent cycle of the identify transaction a data line, the asserted data line corresponding to a particular interrupt routine, and the asserted data line corresponding to an interrupt vector stored in a vector register means in the interrupting device.