EP0348076A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data processing device
Assignee: Fujitsu Services Ltd
•
Filing: 1989-06-08
•
Granted: —
•
Expires: 2009-06-08
Abstract
Abstract A multi-processor data processing system, comprises a plurality of data processing modules. A set of interrupt lines are connected in parallel to all the processing modules. Each processing module has a priority level, and the lowest priority module is selected to act as an interrupt handler, with responsibility for handling all balanced interrupts. Whenever a processing module changes it priority, it clocks to see whether the interrupt handler is still the lowest priority module and, if not, causes the role of interrupt handler to be transferred.
Inventors
- 👤 Terence Michael Cole
- 👤 Geoffrey Poskitt
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 11:33
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26; G06F15/00; G06F15/16; G06F15/163; G06F15/17
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
112 words
A data processing apparatus comprising a plurality of data processing modules, each with a variable priority level, wherein a plurality of interrupt signals are distributed in parallel to all the processing modules, characterised in that, at any given time, one of the modules is designated as an interrupt handler with responsibility for handling all the interrupts, and characterised in that, whenever the priority level of any of the processing modules changes, that processing module determines whether any of the processing modules now has a priority level lower than that of the currently designated interrupt handler and, if so, causes the role of interrupt handler to be transferred to that lower priority module.
Claim 2
Dependent Claim
112 words
A data processing apparatus comprising a plurality of data processing modules, each with a variable priority level, wherein a plurality of interrupt signals are distributed in parallel to all the processing modules, characterised in that, at any given time, one of the modules is designated as an interrupt handler with responsibility for handling all the interrupts, and characterised in that, whenever the priority level of any of the processing modules changes, that processing module determines whether any of the processing modules now has a priority level lower than that of the currently designated interrupt handler and, if so, causes the role of interrupt handler to be transferred to that lower priority module.
Claim 3
Dependent Claim
41 words
Apparatus according to claim 1 wherein each interrupt signal has a priority level associated with it, and wherein, when the processing module currently designated as interrupt handler receives an interrupt, it changes its own priority level to that of the interrupt.
Claim 4
Dependent Claim
23 words
Apparatus according to claim 2 wherein, each processing module is also capable of changing its own priority level voluntarily, without receiving an interrupt.
Claim 5
Dependent Claim
51 words
Apparatus according to any preceding claim wherein, when the role of interrupt handler is transferred, the responsibility for any interrupt that is already active is retained by the processing module that is already handling that interrupt, and responsibility for subsequent occurences of that interrupt are transferred to the new interrupt handler.
Claim 6
Dependent Claim
22 words
Apparatus according to any preceding claim wherein each processing module comprises a mask register for masking selected ones of the interrupt signals.
Claim 7
Dependent Claim
31 words
Apparatus according to claim 5 wherein the role of interrupt handler is transferred by masking out interrupts in the old interrupt handler and unmasking those interrupts in the new interrupt handler.
Claim 8
Dependent Claim
33 words
Apparatus according to claim 5 or 6 wherein a processing module is interrupted whenever the priority level of the highest priority unmasked interrupt signal is greater than the priority level of that module.
Claim 9
Dependent Claim
34 words
Apparatus according to any preceding claim further including a memory, shared among all the processing modules, for storing control information indicating the priority levels of each module and identifying the currently designated interrupt handler.
Claim 10
Dependent Claim
35 words
Apparatus according to claim 8 wherein access to said memory by the processing modules is controlled by a semaphore arrangement permitting only one of the processing modules at a time to access said control information.
References Cited (Backward Citations)
US3421150A
Cited
EP0257348A2
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.