Data processing device for preventing inconsistency of data stored in main memory and cache memory

Claim 2

An address monitoring device for monitoring a process of writing to a main memory by an external device, in which, when an address corresponding to data stored in a cache memory is detected in said write process, stored address data in said cache memory corresponding to said detected write address is invalidated, said address monitoring device comprising: a comparing means for comparing an address of data written into said main memory by said external device with an address of data stored in said cache memory; a masking means for specifying at least one specific bit within the address of the data stored in said cache memory to compare with the address of the data written into said main memory; an invalidating means for invalidating data stored in said cache memory, when a result in said address comparing means is coincidental; a mask bit determining means for determining a number of masked bits for masking in said specific bits; wherein said mask bit determining means determines the number of masked bits for masking in said specific bits in accordance with a data length of said data written into said main memory, and wherein said data are written into said main memory by using a block transfer process.

Claim 3

An address monitoring device as claimed in claim 1, wherein said mask bit determining means comprises a plurality of logic gate circuits, and the number of masked bits for masking in said specific bits are determined by masking control signals supplied to said logic gate circuits.

Claim 4

An address monitoring device as claimed in claim 1, wherein said mask bit determining means comprises a masking address control register, and the number of masked bits for masking in said specific bits are determined by data stored in said masking address control register.

Claim 5

An address monitoring device as claimed in claim 1, wherein said comparing means and said masking means comprise a plurality of logic gate circuits.

Claim 6

An address monitoring device as claimed in claim 1, wherein said invalidating means comprises a tag memory including a valid bit portion.

Claim 7

A data processing device comprising: a bus control unit for transferring data among a main memory and external devices through busses; a memory control unit including a cache memory; an instruction control unit for controlling fetching and decoding of instructions; an instruction execution unit for executing said instructions; a comparing means for comparing an address of data written into a main memory by said external device with an address of data stored in said cache memory; a masking means for specifying at least one specific bit within the address of the data stored in said cache memory to compare with the address of the data written into said main memory; and an invalidating means for invalidating data stored in said cache memory, when a result in said address comparing means being coincidental; a mask bit determining means for determining a number of masked bits for masking in said specific bits; wherein said mask bit determining means determines the number of masked bits for masking in said specific bits in accordance with a data length of said data written into said main memory, and wherein said data are written into said main memory by using a block transfer process.

Claim 8

A data processing device comprising: a bus control unit for transferring data among a main memory and external devices through busses; a memory control unit including a cache memory; an instruction control unit for controlling fetching and decoding of instructions; an instruction execution unit for executing said instructions; a comparing means for comparing an address of data written into a main memory by said external device with an address of data stored in said cache memory; a masking means for specifying at least one specific bit within the address of the data stored in said cache memory to compare with the address of the data written into said main memory; and an invalidating means for invalidating data stored in said cache memory, when a result in said address comparing means being coincidental; a mask bit determining means for determining a number of masked bits for masking in said specific bits; wherein said mask bit determining means determines the number of masked bits for masking in said specific bits in accordance with a data length of said data written into said main memory, and wherein said data are written into said main memory by using a block transfer process.

Claim 9

A data processing device as claimed in claim 6, wherein said mask bit determining means comprises a plurality of logic gate circuits, and the number of masked bits for masking in said specific bits are determined by masking control signals supplied to said logic gate circuits.

Claim 10

A data processing device as claimed in claim 6, wherein said mask bit determining means comprises a masking address control register, and the number of masked bits for masking in said specific bits are determined by data stored in said masking address control register.

Claim 11

A data processing device as claimed in claim 6, wherein said comparing means and said masking means comprise a plurality of logic gate circuits.

Claim 12

A data processing device as claimed in claim 6, wherein said invalidating means comprises a tag memory including a valid bit portion.

Claim 13

A data processing device as claimed in claim 6, wherein said external device writing data into said main memory is one of a further data processing device and a direct memory access controller, and is connected to said data processing device and said main memory through a system bus.

Claim 14

A data processing system having a data processing device, external devices, a main memory, and a system bus for connecting said data processing device, said external devices, and said main memory, said data processing device comprising: a bus control unit for transferring data among said main memory and said external devices through a bus; a memory control unit including a cache memory; an instruction control unit for controlling fetching and decoding of instructions; an instruction execution unit for executing said instructions; a comparing means for comparing an address of data written into a main memory by an external device with an address of data stored in said cache memory; a masking means for specifying at least one specific bit within the address of the data stored in said cache memory to compare with the address of the data written into said main memory; and an invalidating means for invalidating data stored in said cache memory, when a result in said address comparing means is coincidental; a mask bit determining means for determining a number of masked bits for masking in said specific bits; wherein said mask bit determining means determines the number of masked bits for masking in said specific bits in accordance with a data length of said data written into said main memory, and wherein said data are written into said main memory by using a block transfer process.

Claim 15

A data processing system having a data processing device, external devices, a main memory, and a system bus for connecting said data processing device, said external devices, and said main memory, said data processing device comprising: a bus control unit for transferring data among said main memory and said external devices through a bus; a memory control unit including a cache memory; an instruction control unit for controlling fetching and decoding of instructions; an instruction execution unit for executing said instructions; a comparing means for comparing an address of data written into a main memory by an external device with an address of data stored in said cache memory; a masking means for specifying at least one specific bit within the address of the data stored in said cache memory to compare with the address of the data written into said main memory; and an invalidating means for invalidating data stored in said cache memory, when a result in said address comparing means is coincidental; a mask bit determining means for determining a number of masked bits for masking in said specific bits; wherein said mask bit determining means determines the number of masked bits for masking in said specific bits in accordance with a data length of said data written into said main memory, and wherein said data are written into said main memory by using a block transfer process.

Claim 16

A data processing system as claimed in claim 12, wherein said data processing device further comprises a mask bit determining means for determining a number of masked bits for masking in said specific bits.

Claim 17

A monolithic microprocessor formed in a single semiconductor body, said monolithic microprocessor comprising: a built-in cache memory; an instruction execution means, for executing an instruction and outputting a write address for accessing one of said built-in cache memory and a main memory; and an address monitoring device comprising: a comparing means for comparing an address of data written into a main memory by an external device with an address of data stored in a cache memory; a masking means for specifying at least one specific bit within the address of the data stored in said cache memory to compare with the address of the data written into said main memory; and an invalidating means for invalidating data stored in said cache memory, when a result in said address comparing means is coincidental; a mask bit determining means for determining a number of masked bits for masking in said specific bits; wherein said mask bit determining means determines the number of masked bits for masking in said specific bits in accordance with a data length of said data written into said main memory, and wherein said data are written into said main memory by using a block transfer process.

Claim 18

A monolithic microprocessor formed in a single semiconductor body, said monolithic microprocessor comprising: a built-in cache memory; an instruction execution means, for executing an instruction and outputting a write address for accessing one of said built-in cache memory and a main memory; and an address monitoring device comprising: a comparing means for comparing an address of data written into a main memory by an external device with an address of data stored in a cache memory; a masking means for specifying at least one specific bit within the address of the data stored in said cache memory to compare with the address of the data written into said main memory; and an invalidating means for invalidating data stored in said cache memory, when a result in said address comparing means is coincidental; a mask bit determining means for determining a number of masked bits for masking in said specific bits; wherein said mask bit determining means determines the number of masked bits for masking in said specific bits in accordance with a data length of said data written into said main memory, and wherein said data are written into said main memory by using a block transfer process.

Claim 19

A monolithic microprocessor as claimed in claim 14, wherein said mask bit determining means comprises a plurality of logic gate circuits, and the number of masked bits for masking in said specific bits are determined by masking control signals supplied to said logic gate circuits.

Claim 20

A monolithic microprocessor as claimed in claim 14, wherein said mask bit determining means comprises a masking address control register, and the number of masked bits for masking in said specific bits are determined by data stored in said masking address control register.

Claim 21

A monolithic microprocessor as claimed in claim 14, wherein said comparing means and said masking means comprise a plurality of logic gate circuits.

Claim 22

A monolithic microprocessor as claimed in claim 14, wherein said invalidating means comprises a tag memory including a valid bit portion.

Claim 23

A monolithic microprocessor as claimed in claim 14, wherein said external device writing data into said main memory is one of a further monolithic microprocessor and a direct memory access controller, and is connected to said data processing device and said main memory through a system bus.