Buffer storage control system having buffer storage unit comparing operand (OP) side and instruction fetch (IF) side tag storages

Claim 2

A buffer storage control system, incorporated into a multiprocessor, comprising: a plurality of central processing units, a main storage unit storing many data blocks composed of operand data and instruction data, and a main storage control unit connected to said central processor units and said main storage unit and operative to control data transfer between the main storage unit and the central processing units via bus lines; each of the central processing units including a buffer storage unit comprising a tag storage unit and a data storage unit, the tag storage unit including an operand (OP) side tag storage and an instruction fetch (IF) side tag storage, the data storage unit including an OP side data storage storing the operand data and an IF side data storage storing the instruction data; the main storage control unit having a plurality of buffer storage address memories one for each of said central processing units, each buffer storage address memory including an OP side memory and IF side memory; said buffer storage control system being operated using an identification flag, having a value identifying whether an address corresponds to operand data or instruction data, which is produced, during a fetch operation, in any one of said central processing units and transferred with address data for the fetch, via a corresponding one of said bus lines, to the main storage control unit; the identification flag being also produced, during a store operation, by the main storage control unit and transferred with a address to be invalidated, via a corresponding one of said bus lines, to the central processing unit concerned, allowing the central processing unit to determine whether data to be invalidated is operand data or instruction data; the value of said identification flag indicates, during the fetch operation, whether the address being fetched is to be recorded in said OP side or said IF side memory of said buffer storage address memory; and the value of said identification flag indicates, during the store operation by a first one of said central processing units, whether the address being invalidated is to be applied to said OP side or said IF side tag storage of a second one of said central processing units to invalidate the identical address in the indicated side tag storage of the second one of said central processing units.

Claim 3

A system as set forth in claim 1, wherein each central processing unit includes an instruction unit, an execution unit and a storage control unit, and during said fetch operation, said identification flag is produced by one of said central processing units through the storage control unit, when the instruction unit issues a request for operand fetch or a request for instruction fetch, together with the address for fetch, and thereby both the identification flag, indicating OP side fetch or IF side fetch, and the related address for fetch are transferred to the main storage control unit.

Claim 4

A system as set forth in claim 2, wherein each of said OP side memories includes an OP side logic gate and each of said IF side memories includes an IF side logic gate, either the OP side logic gate or the IF side logic gate being opened in accordance with the identification flag to allow the related address for fetch to pass therethrough and be recorded in the corresponding OP side memory or IF side memory.

Claim 5

A system as set forth in claim 3, further comprising a decoder, connected to said main storage control unit and OP side and If side logic gates, for decoding the value of the identification flag and wherein said OP side logic gate or said IF side logic gate is opened by said decoder which operates to select one of the logic gates in accordance with the identification flag.

Claim 6

A system as set forth in claim 4, wherein said address for fetch includes both upper bits and lower bits, and the upper and lower bits passing through the OP side or IF side logic gate opened by said decoder, the lower bits being used for accessing the corresponding tag or data storage unit to specify the address at which the upper bits are recorded, and the upper bits specifying the address for fetch in terms of a main storage unit address.

Claim 7

A system as set forth in claim 1, wherein each central processing unit includes an instruction unit, an execution unit and a storage control unit, and each OP side and IF side memory includes a comparing circuit having first and second inputs, and during said store operation, the address for buffer storage is provided by any one of the central processing units through the storage control unit, to store the related store data in the main storage unit at said address for storage, while the address for storage is applied to the main storage control unit to determine whether an address identical to the address for storage exists in any of said OP and IF side memories, by means of the comparing circuits, the comparing circuits receive, at each first input, said address for storage, at the second inputs respective address data from the respective OP side and IF side memory, and said identification flag indicative of the OP side or IF side being produced by the OP side comparing circuit or the IF side comparing circuit, if coincidence of the two addresses, at the first and second inputs thereof, occurs.

Claim 8

A system as set forth in claim 6, wherein each of said OP side tag storage units including an OP side logic gate and each of said IF side tag storage units including an IF side logic gate, either the OP side logic gate or the IF side logic gate is opened in accordance with the identification flag to allow the related address for storage to pass therethrough and invalidate the identical address applied in the corresponding OP side tag storage or IF side tag storage.

Claim 9

A system as set forth in claim 7, further including an OP side flip-flop and an IF side flip-flop and wherein said OP side logic gate or said IF side logic gate is opened by the output from the OP side flip-flop or the IF side flip-flop, the OP side flip-flop is set by the corresponding OP side comparing circuit when the coincidence is detected by the corresponding OP side comparing circuit, and the IF side flip-flop is set by the corresponding IF side comparing circuit when said coincidence is detected by the corresponding IF side comparing circuit, the outputs from these flip-flops forming said identification flag.

Claim 10

A system as set forth in claim 8, wherein said address for storage included both upper bits and lower bits, the upper bits specifying the address for storage, in terms of a main storage unit address, and being applied to the first input of each said comparing circuit, the lower bits passing through the respective opened logic gate and accessing the corresponding OP side or IF side tag storage unit for invalidation of the accessed address for storage.

Claim 11

A buffer storage control system connected to a main storage unit, comprising: a central processing unit (CPU), comprising: storage control means for producing a fetch address for fetching instructions and data from said main storage unit and an identification flag indicating whether the fetch address is an instruction or data address; CPU determination means, connected to said storage control means, for indicating that the fetch address is an instruction or data address in dependence upon the identification flag; CPU instruction tag storage means, connected to said CPU determination means, for storing as a CPU instruction tag, the fetch address of a fetched instruction fetched from the main storage unit in dependence upon the indication of an instruction fetch address by said CPU determination means; instruction storage means, connected to said CPU tag storage means and said main storage unit, for storing the fetched instruction, fetched from the main storage unit, in correspondence with the CPU instruction tag and in dependence upon the indication of an instruction fetch address by said determination means; CPU data tag storage means, connected to said CPU determination means, for storing as a CPU data tag the fetch address of fetched data fetched from the main storage unit in dependence upon the indication of a data fetch address by said determination means; and data storage means, connected to said CPU data tag storage means and said main storage unit, for storing fetched data, fetched from the main storage unit, in correspondence with the CPU data tag and in dependence upon the indication of a data fetch address by said determination means; and a main storage control unit (MCU) connected to said central processing unit storage control means to receive the fetch address and the identification flag, said main storage control unit comprising: MCU determination means, connected to said storage control means, for indicating that the fetch address is an instruction or data address in dependence upon the identification flag; MCU instruction tag storage means, coupled to said MCU determination means, for storing as an MCU instruction tag the fetch address of the fetched instruction in dependence upon the indication of an instruction fetch address by said MCU determination means; and MCU data tag storage means, coupled to said MCU determination means, for storing as an MCU data tag the fetch address of the fetched data in dependence upon the indication of a data fetch address by said MCU determination means.

Claim 12

A buffer storage control system connected to a main storage unit, comprising: a central processing unit (CPU), comprising: storage control means for producing a fetch address for fetching instructions and data from said main storage unit and an identification flag indicating whether the fetch address is an instruction or data address; CPU determination means, connected to said storage control means, for indicating that the fetch address is an instruction or data address in dependence upon the identification flag; CPU instruction tag storage means, connected to said CPU determination means, for storing as a CPU instruction tag, the fetch address of a fetched instruction fetched from the main storage unit in dependence upon the indication of an instruction fetch address by said CPU determination means; instruction storage means, connected to said CPU tag storage means and said main storage unit, for storing the fetched instruction, fetched from the main storage unit, in correspondence with the CPU instruction tag and in dependence upon the indication of an instruction fetch address by said determination means; CPU data tag storage means, connected to said CPU determination means, for storing as a CPU data tag the fetch address of fetched data fetched from the main storage unit in dependence upon the indication of a data fetch address by said determination means; and data storage means, connected to said CPU data tag storage means and said main storage unit, for storing fetched data, fetched from the main storage unit, in correspondence with the CPU data tag and in dependence upon the indication of a data fetch address by said determination means; and a main storage control unit (MCU) connected to said central processing unit storage control means to receive the fetch address and the identification flag, said main storage control unit comprising: MCU determination means, connected to said storage control means, for indicating that the fetch address is an instruction or data address in dependence upon the identification flag; MCU instruction tag storage means, coupled to said MCU determination means, for storing as an MCU instruction tag the fetch address of the fetched instruction in dependence upon the indication of an instruction fetch address by said MCU determination means; and MCU data tag storage means, coupled to said MCU determination means, for storing as an MCU data tag the fetch address of the fetched data in dependence upon the indication of a data fetch address by said MCU determination means.

Claim 13

A buffer storage control system connected to a main storage unit, comprising: a central processing unit (CPU), comprising: storage control means for producing a storage address and an identification flag indicating whether the storage address is an instruction or data address; and a main storage control unit (MCU) connected to said central processing unit storage control means to receive the storage address and the identification flag, said main storage control unit comprising: MCU determination means, connected to said storage control means, for indicating that the storage address is an instruction or data address in dependence upon the identification flag; MCU instruction tag storage means, connected to said MCU determination means and said storage control means, for reading out the contents of an instruction tag in dependence upon the indication by said MCU determination means and said storage address; instruction storage address comparison means, connected to said MCU instruction tag storage means and said storage control means, for comparing the contents of the instruction tag readout with the storage address and producing an instruction invalidation signal when coincidence occurs; MCU data tag storage means, connected to said MCU determination means and said storage control means, for reading out the contents of a data tag in dependence upon the indication by said determination means and said storage address; and data storage address comparison means, connected to said MCU data tag storage means and said storage control means, for comparing the contents of the data tag read out with the storage address and producing a data invalidation signal when coincidence occurs; and said central processing unit further comprising: CPU determination means, connected to said instruction and data address storage comparison means, for indicating an instruction or data address in dependence upon the data and instruction invalidation signals; instruction tag storage means, connected to said storage control means and said CPU determination means, for invalidating an instruction tag, including the address of a stored instruction tag corresponding to the storage address, in dependence upon the determination by said CPU determination means; and data tag storage means, connected to said storage control means and said CPU determination means, for invalidating a data tag, including the address of a stored data tag corresponding to the storage address, in dependence upon the determination by said CPU determination means.

Claim 14

A buffer storage control system connected to a main storage unit, comprising: a central processing unit (CPU), comprising: storage control means for producing a storage address and an identification flag indicating whether the storage address is an instruction or data address; and a main storage control unit (MCU) connected to said central processing unit storage control means to receive the storage address and the identification flag, said main storage control unit comprising: MCU determination means, connected to said storage control means, for indicating that the storage address is an instruction or data address in dependence upon the identification flag; MCU instruction tag storage means, connected to said MCU determination means and said storage control means, for reading out the contents of an instruction tag in dependence upon the indication by said MCU determination means and said storage address; instruction storage address comparison means, connected to said MCU instruction tag storage means and said storage control means, for comparing the contents of the instruction tag readout with the storage address and producing an instruction invalidation signal when coincidence occurs; MCU data tag storage means, connected to said MCU determination means and said storage control means, for reading out the contents of a data tag in dependence upon the indication by said determination means and said storage address; and data storage address comparison means, connected to said MCU data tag storage means and said storage control means, for comparing the contents of the data tag read out with the storage address and producing a data invalidation signal when coincidence occurs; and said central processing unit further comprising: CPU determination means, connected to said instruction and data address storage comparison means, for indicating an instruction or data address in dependence upon the data and instruction invalidation signals; instruction tag storage means, connected to said storage control means and said CPU determination means, for invalidating an instruction tag, including the address of a stored instruction tag corresponding to the storage address, in dependence upon the determination by said CPU determination means; and data tag storage means, connected to said storage control means and said CPU determination means, for invalidating a data tag, including the address of a stored data tag corresponding to the storage address, in dependence upon the determination by said CPU determination means.