US5376561A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density electronic circuit modules
Assignee: Kopin Corp
•
Filing: 1992-04-24
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Granted: 1994-12-27
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Expires: 2012-04-24
Abstract
Abstract The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.
Inventors
- 👤 Duv-Pach Vu
- 👤 Brenda Dingle
- 👤 Ngwe Cheong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:02
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D86/021; H10D86/0214; A; A61; A61B; A61B3/00; A61B3/10; A61B3/113; G; G02; G02B; G02B27/00; G02B27/0093; G02B27/01; G02B27/017; G02B27/0172; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1335; G02F1/133526; G02F1/1345; G02F1/13454; G02F1/136; G02F1/1362; G02F1/136209; G02F1/136277; G09; G09G; G09G3/00; G09G3/20; G09G3/22; G09G3/30; G09G3/34; G09G3/36; H04; H04N; H04N5/00; H04N5/74; H04N5/7416; H04N5/7441; H04N9/00; H04N9/12; H04N9/31; H04N9/3141; H05; H05B; H05B33/00; H05B33/12; H10D30/00; H10D30/60; H10D30/67; H10D30/6758; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D86/40; H10D86/60; H10D88/00; H10D88/01; H10D89/00; H10H; H10H29/00; H10H29/10; H10H29/14; H10H29/142; H10W; H10W72/00; H10W72/01; H10W72/0198; H10W90/00; G02B27/0101; G02B2027/0132; G02B2027/0138; G02B27/0179; G02B2027/0187; G02B2027/0192; G02B2027/0198; G02B5/00; G02B5/30; G02F1/13336; G02F1/1347; G02F1/13471; G02F1/13473; G02F1/13613; G02F2202/00; G02F2202/10; G02F2202/105; G09G2300/00; G09G2300/02; G09G2300/023; G09G2300/08; G09G2300/0809; G09G2300/0842; G09G2320/00; G09G2320/02; G09G2320/0233; G09G2320/04; G09G2320/041; G09G2320/043; G09G2340/00; G09G2340/04; G09G2340/0464; G09G2370/00; G09G2370/04; G09G2370/042; G09G3/32; G09G3/3607; G09G3/3611; G09G3/3614; G09G3/3648; H01; H01S; H01S5/00; H01S5/02; H01S5/0206; H01S5/0217; H01S5/40; H01S5/42; H01S5/423; H04N5/66; H04N5/70; H04N5/7475; H04N5/7491; H10D30/6729; H10D30/673; H10D30/6733; H10D30/6734; H10P; H10P72/00; H10P72/70; H10P72/74; H10P72/743; H10P72/7432; H10P72/7434; Y; Y10; Y10S; Y10S148/00; Y10S148/135; Y10S148/15
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
157 words
A method of fabricating a vertical bipolar transistor comprising: providing a layer of silicon over an insulating layer to provide an SOI structure; doping the silicon layer to produce a collector region and an emitter region, the collector and emitter regions being of a first conductivity type and separated by a base region of a second conductivity type such that a first conductivity junction is positioned between the collector region and base region; attaching conductive contacts to the collector, base and emitter regions on a first side of the silicon layer; transferring the SOI structure from a first substrate onto a second substrate, the SOI structure being bonded to the second substrate with an adhesive; removing a region of the insulating layer exposing a backside region on a second side of the silicon layer opposite the first side; and forming a metal layer over the backside region of the silicon layer to provide a vertical bipolar transistor.
Claim 2
Independent Claim
157 words
A method of fabricating a vertical bipolar transistor comprising: providing a layer of silicon over an insulating layer to provide an SOI structure; doping the silicon layer to produce a collector region and an emitter region, the collector and emitter regions being of a first conductivity type and separated by a base region of a second conductivity type such that a first conductivity junction is positioned between the collector region and base region; attaching conductive contacts to the collector, base and emitter regions on a first side of the silicon layer; transferring the SOI structure from a first substrate onto a second substrate, the SOI structure being bonded to the second substrate with an adhesive; removing a region of the insulating layer exposing a backside region on a second side of the silicon layer opposite the first side; and forming a metal layer over the backside region of the silicon layer to provide a vertical bipolar transistor.
Claim 3
Dependent Claim
24 words
The method of claim 1 wherein the providing step further comprises recrystallizing a non-single crystal silicon material to form a single crystal silicon layer.
Claim 4
Dependent Claim
12 words
The method of claim 1 wherein the insulating layer comprises an oxide.
Claim 5
Dependent Claim
27 words
The method of claim 1 wherein the step of doping the silicon layer to provide the collector region comprises doping a layer positioned on the insulating layer.
Claim 6
Dependent Claim
30 words
The method of claim 1 wherein the step of doping the silicon layer to provide the emitter region comprises doping the silicon layer in a position over the collector region.
Claim 7
Dependent Claim
17 words
The method of claim 1 wherein the metal forming step further comprises sintering the formed metal layer.
Claim 8
Dependent Claim
23 words
The method of claim 1 further comprising implanting a further dopant in the exposed back region prior to formation of the metal layer.
Claim 9
Dependent Claim
29 words
The method of claim 1 wherein the step of removing a region of the insulating layer is preceded by patterning the insulating layer such that predetermined regions are removed.
Claim 10
Dependent Claim
12 words
The method of claim 1 wherein the completed device retains the adhesive.
Claim 11
Independent Claim
156 words
A method of fabricating a vertical bipolar transistor comprising: providing a layer of single crystal silicon over an insulating layer and an underlying substrate; doping the silicon layer to produce a collector region and an emitter region, the collector and emitter regions being of a first conductivity type and separated by a base region of a second conductivity type such that a first conductivity junction is positioned between the collector region and base region; attaching conductive contacts to the collector, base and emitter regions on a first side of the silicon layer; transferring the doped silicon layer and insulating layer onto a second substrate, the silicon layer being bonded to the second substrate with an adhesive comprising a cycloaliphatic anhydride; removing a region of the insulating layer exposing a backside region on a second side of the silicon layer opposite the first side; and forming a metal layer over the backside region of the silicon layer.
Claim 12
Independent Claim
156 words
A method of fabricating a vertical bipolar transistor comprising: providing a layer of single crystal silicon over an insulating layer and an underlying substrate; doping the silicon layer to produce a collector region and an emitter region, the collector and emitter regions being of a first conductivity type and separated by a base region of a second conductivity type such that a first conductivity junction is positioned between the collector region and base region; attaching conductive contacts to the collector, base and emitter regions on a first side of the silicon layer; transferring the doped silicon layer and insulating layer onto a second substrate, the silicon layer being bonded to the second substrate with an adhesive comprising a cycloaliphatic anhydride; removing a region of the insulating layer exposing a backside region on a second side of the silicon layer opposite the first side; and forming a metal layer over the backside region of the silicon layer.
Claim 13
Dependent Claim
32 words
The method of claim 10 wherein the step of applying conductive contacts is followed by the step of transferring the doped silicon layer from a first substrate to a second glass substrate.
Claim 14
Dependent Claim
24 words
The method of claim 10 wherein the providing step further comprises recrystallizing a non-single crystal silicon material to form a single crystal silicon layer.
Claim 15
Dependent Claim
12 words
The method of claim 10 wherein the insulating layer comprises an oxide.
Claim 16
Independent Claim
136 words
A method of fabricating a vertical bipolar transistor comprising: providing a layer of non-single crystal silicon over an insulating layer; recrystallizing the non-single crystal layer to form a single crystal silicon layer; doping the silicon layer to produce a collector region and an emitter region, the collector and emitter regions being of a first conductivity type and separated by a base region of a second conductivity type such that a first conductivity junction is positioned between the collector region and base region; attaching conductive contacts to the collector, base and emitter regions on a first side of the silicon layer; removing a region of the insulating layer exposing a backside region on a second side of the silicon layer opposite the first side; and forming a metal layer over the backside region of the silicon layer.
Claim 17
Independent Claim
136 words
A method of fabricating a vertical bipolar transistor comprising: providing a layer of non-single crystal silicon over an insulating layer; recrystallizing the non-single crystal layer to form a single crystal silicon layer; doping the silicon layer to produce a collector region and an emitter region, the collector and emitter regions being of a first conductivity type and separated by a base region of a second conductivity type such that a first conductivity junction is positioned between the collector region and base region; attaching conductive contacts to the collector, base and emitter regions on a first side of the silicon layer; removing a region of the insulating layer exposing a backside region on a second side of the silicon layer opposite the first side; and forming a metal layer over the backside region of the silicon layer.
Claim 18
Dependent Claim
31 words
The method of claim 14 wherein the step of applying conductive contacts is followed by the step of transferring the doped silicon layer from a first substrate to a second substrate.
Claim 19
Dependent Claim
23 words
The method of claim 15 wherein the transferring step further comprises bonding the doped silicon layer to the second substrate with an adhesive.
Claim 20
Dependent Claim
24 words
The method of claim 14 wherein the providing step further comprises recrystallizing a non-single crystal silicon material to form a single crystal silicon layer.
Claim 21
Dependent Claim
12 words
The method of claim 14 wherein the insulating layer comprises an oxide.
Claim 22
Dependent Claim
11 words
The method of claim 14 further comprising sintering the metal layer.
Claim 23
Independent Claim
142 words
A method of fabricating a vertical bipolar transistor comprising: providing an insulating layer on a semiconductor substrate; providing a layer of silicon over the insulating layer; doping the silicon layer to produce a collector region and an emitter region, the collector and emitter regions being of a first conductivity type and separated by a base region of a second conductivity type such that a first conductivity junction is positioned between the collector region and base region; attaching conductive contacts to the collector, base and emitter regions on a first side of the silicon layer; transferring the doped silicon layer and insulating layer to a second substrate; removing a region of the insulating layer exposing a backside region on a second side of the silicon layer opposite the first side; and forming a metal layer over the backside region of the silicon layer.
Claim 24
Independent Claim
142 words
A method of fabricating a vertical bipolar transistor comprising: providing an insulating layer on a semiconductor substrate; providing a layer of silicon over the insulating layer; doping the silicon layer to produce a collector region and an emitter region, the collector and emitter regions being of a first conductivity type and separated by a base region of a second conductivity type such that a first conductivity junction is positioned between the collector region and base region; attaching conductive contacts to the collector, base and emitter regions on a first side of the silicon layer; transferring the doped silicon layer and insulating layer to a second substrate; removing a region of the insulating layer exposing a backside region on a second side of the silicon layer opposite the first side; and forming a metal layer over the backside region of the silicon layer.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-12-26 | 1998-06-27 | 1998-12-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-26 | 2002-06-27 | 2002-12-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-26 | 2006-06-27 | 2006-12-27 | $7700.00 | Window Closed / Lapsed |