Patent US5374833A successfully refreshed from Google Patents.
US5374833A
Expired / Lapsed
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Structure for suppression of field inversion caused by charge build-up in the dielectric
Assignee: NXP BV
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Filing: 1991-10-11
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Granted: 1994-12-20
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Expires: 2011-10-11
Abstract
Abstract The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.
Inventors
- 👤 Subhash R. Nariani
- 👤 Vivek Jain
- 👤 Dipankar Pramanik
- 👤 Kuang-Yeh Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 05:38
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/40; H10W74/481; H10P; H10P14/00; H10P14/60; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10W74/43; H10B; H10B69/00; Y; Y10; Y10S; Y10S438/00; Y10S438/91; Y10S438/958
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
93 words
An integrated circuit comprising: a substrate; a plurality of electrical devices formed on said substrate; isolation means provided between each of said electrical devices; at least one metallization layer for interconnecting the electrical devices; a first dielectric layer located adjacent said metallization layer; a first layer of amorphous silicon formed on at least a first side of said first dielectric layer between said at least one metallization layer and said first dielectric layer; and another layer of amorphous silicon formed on a second side of said first dielectric layer opposite said first side.
Claim 2
Dependent Claim
93 words
An integrated circuit comprising: a substrate; a plurality of electrical devices formed on said substrate; isolation means provided between each of said electrical devices; at least one metallization layer for interconnecting the electrical devices; a first dielectric layer located adjacent said metallization layer; a first layer of amorphous silicon formed on at least a first side of said first dielectric layer between said at least one metallization layer and said first dielectric layer; and another layer of amorphous silicon formed on a second side of said first dielectric layer opposite said first side.
Claim 3
Dependent Claim
100 words
An integrated circuit comprising: a substrate; a plurality of electrical devices formed on said substrate; isolation means provided between each of said electrical devices; at least one metallization layer for interconnecting the electrical devices; a first dielectric layer located adjacent said metallization layer; a layer of amorphous silicon formed on at least a first side of said first dielectric layer between said at least one metallization layer and said first dielectric layer; and an intermetal oxide sandwich which includes upper and lower oxide layers, said first dielectric layer being a spin-on-glass layer located between said upper and lower oxide layers.
Claim 4
Dependent Claim
100 words
An integrated circuit comprising: a substrate; a plurality of electrical devices formed on said substrate; isolation means provided between each of said electrical devices; at least one metallization layer for interconnecting the electrical devices; a first dielectric layer located adjacent said metallization layer; a layer of amorphous silicon formed on at least a first side of said first dielectric layer between said at least one metallization layer and said first dielectric layer; and an intermetal oxide sandwich which includes upper and lower oxide layers, said first dielectric layer being a spin-on-glass layer located between said upper and lower oxide layers.
Claim 5
Dependent Claim
97 words
An integrated circuit comprising: a substrate; a plurality of electrical devices formed on said substrate; isolation means provided between each of said electrical devices; at least one metallization layer for interconnecting the electrical devices; a first dielectric layer located adjacent said metallization layer; and a layer of amorphous silicon formed on at least a first side of said first dielectric layer between said at least one metallization layer and said first dielectric layer, wherein said first dielectric is a BPSG layer formed on said isolation means between said isolation means and said at least one metallization layer.
Claim 6
Dependent Claim
97 words
An integrated circuit comprising: a substrate; a plurality of electrical devices formed on said substrate; isolation means provided between each of said electrical devices; at least one metallization layer for interconnecting the electrical devices; a first dielectric layer located adjacent said metallization layer; and a layer of amorphous silicon formed on at least a first side of said first dielectric layer between said at least one metallization layer and said first dielectric layer, wherein said first dielectric is a BPSG layer formed on said isolation means between said isolation means and said at least one metallization layer.
Claim 7
Dependent Claim
28 words
An integrated circuit according to claim 2 further comprising: another layer of amorphous silicon formed on a second side of said first dielectric layer opposite said first side.
Claim 8
Dependent Claim
27 words
An integrated circuit according to claim 3 further comprising: another layer of amorphous silicon formed on a second side of said BPSG layer opposite said first side.
Claim 9
Dependent Claim
31 words
An integrated circuit according to claim 3 further comprising: another layer of amorphous silicon formed on a second side of said BPSG layer between said isolation means and said BPSG layer.
Claim 10
Dependent Claim
57 words
An integrated circuit according to claim 6 further comprising: a second dielectric layer located adjacent said at least one metallization layer; and a third layer of amorphous silicon formed on said first side of said BPSG layer, said third layer of amorphous silicon being formed between said second dielectric layer and said at least one metallization layer.
Claim 11
Dependent Claim
96 words
An integrated circuit comprising: a substrate; a plurality of electrical devices formed on said substrate; isolation means provided between each of said electrical devices; at least one metallization layer for interconnecting the electrical devices; a first dielectric layer located adjacent said metallization layer; and a layer of amorphous silicon formed on said isolation means and being located on at least one side of said first dielectric layer between said first dielectric layer and said isolation means, wherein said first dielectric is a BPSG layer located between said isolation means and said at least one metallization layer.
Claim 12
Dependent Claim
96 words
An integrated circuit comprising: a substrate; a plurality of electrical devices formed on said substrate; isolation means provided between each of said electrical devices; at least one metallization layer for interconnecting the electrical devices; a first dielectric layer located adjacent said metallization layer; and a layer of amorphous silicon formed on said isolation means and being located on at least one side of said first dielectric layer between said first dielectric layer and said isolation means, wherein said first dielectric is a BPSG layer located between said isolation means and said at least one metallization layer.
Claim 13
Dependent Claim
42 words
An integrated circuit according to claim 8 further comprising: another layer of amorphous silicon formed on another side of said BPSG layer opposite said one side, said another layer being formed between said BPSG layer and said at least one metallization layer.
Claim 14
Dependent Claim
41 words
An integrated circuit according to claim 1 further comprising: a nitride passivation layer, said first layer of amorphous silicon neutralizing charges created in said first dielectric layer due to a reaction of said nitride passivation layer with said first dielectric layer.
Claim 15
Dependent Claim
18 words
An integrated circuit according to claim 1 wherein said first dielectric layer is formed of an organic material.
Claim 16
Dependent Claim
15 words
An integrated circuit according to claim 11 wherein said organic material is a spin-on-glass layer.
Claim 17
Dependent Claim
16 words
An integrated circuit according to claim 10 wherein said first dielectric layer is a spin-on-glass layer.
Claim 18
Dependent Claim
16 words
An integrated circuit according to claim 10 wherein said first dielectric layer is a BPSG layer.
Claim 19
Dependent Claim
39 words
An integrated circuit according to claim 2 further comprising: a nitride passivation layer, said layer of amorphous silicon neutralizing charges created in said first dielectric layer due to a reaction of said nitride passivation layer with said dielectric layer.
Claim 20
Dependent Claim
39 words
An integrated circuit according to claim 3 further comprising: a nitride passivation layer, said layer of amorphous silicon neutralizing charges created in said first dielectric layer due to a reaction of said nitride passivation layer with said dielectric layer.
Claim 21
Dependent Claim
26 words
An integrated circuit according to claim 8, further comprising: a nitride passivation layer, said layer of amorphous silicon neutralizing charges created by said nitride passivation layer.
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