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US5373178A Expired / Lapsed US ⏱️ 0.0 years remaining

MOSFET with sidewall spacer on gate section

Assignee: JFE Steel Corp
•
Filing: 1993-07-26
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Granted: 1994-12-13
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Expires: 2013-07-26
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Abstract

Abstract After forming a low concentration impurity layer by ion implanting an impurity into a semiconductor substrate 1 by using a gate electrode 7 on the semiconductor substrate 1 as a mask, side walls composed of films having a large etching resistivity with respect to an interlayer dielectric film 13 are formed on side surfaces of the gate electrode 7 and a gate oxide film 6 located beneath the gate electrode 7. Subsequently, the interlayer dielectric film 13 is formed over the whole surface, and a contact hole 18 having a part of side walls constituted by the first-mentioned side walls 8 and a field oxide film 2 is formed. A high concentration impurity layer is formed by implanting an impurity through the contact hole 18.

Inventors

  • 👤 Makoto Motoyoshi
  • 👤 Eita Kinoshita

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 03:48
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/0186; H10D84/02; H10D84/03; H10D84/038; H10W; H10W20/00; H10W20/01; H10W20/071; Y; Y10; Y10S; Y10S257/00; Y10S257/90

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 182 words
A semiconductor device comprising: a gate electrode formed on a gate oxide film on a semiconductor substrate; a source and a drain, each of the source and the drain being composed of a low concentration impurity layer and a high concentration impurity layer; side walls formed on side surfaces of a gate section, the gate section including the gate electrode and the gate oxide film; an interlayer dielectric film formed directly on the gate electrode, the source, the drain, a field oxide, and the side walls; and contact holes opened into the interlayer dielectric film for respectively connecting wiring to the source and the drain, wherein the side walls are formed with films having a property in which an etching resistivity with respect to the interlayer dielectric film is large, and the side walls of the gate section constitute at least a part of side walls of each of the contact holes, and the high concentration impurity layer of each of the source and the drain are formed with respect to a corresponding one of the contact holes in a self-aligned manner.
Claim 2
Dependent Claim 182 words
A semiconductor device comprising: a gate electrode formed on a gate oxide film on a semiconductor substrate; a source and a drain, each of the source and the drain being composed of a low concentration impurity layer and a high concentration impurity layer; side walls formed on side surfaces of a gate section, the gate section including the gate electrode and the gate oxide film; an interlayer dielectric film formed directly on the gate electrode, the source, the drain, a field oxide, and the side walls; and contact holes opened into the interlayer dielectric film for respectively connecting wiring to the source and the drain, wherein the side walls are formed with films having a property in which an etching resistivity with respect to the interlayer dielectric film is large, and the side walls of the gate section constitute at least a part of side walls of each of the contact holes, and the high concentration impurity layer of each of the source and the drain are formed with respect to a corresponding one of the contact holes in a self-aligned manner.
Claim 3
Dependent Claim 29 words
A semiconductor device according to claim 1, wherein at least a part of the side walls of each of the contact holes is composed of a field oxide film.
Claim 4
Dependent Claim 22 words
A semiconductor device according to claim 1, wherein the side walls of the gate section are composed of a silicon nitride film.
Claim 5
Dependent Claim 21 words
A semiconductor device according to claim 1, wherein the side walls of the gate section are composed of polycrystalline silicon films.

References Cited (Backward Citations)

US4971922A Cited
US4786609A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-12-12 1998-06-13 1998-12-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-12-12 2002-06-13 2002-12-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-12-12 2006-06-13 2006-12-13 $7700.00 Window Closed / Lapsed

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