Dual hardware channels and hardware context switching in a graphics rendering processor

Claim 1

A real-time, high speed display system comprising: at least one stored program computer for generating a plurality of independent display lists, each display list including a plurality of graphic instructions; at least first high priority and second low priority independent First In First Out (FIFO) Buffers for storing a plurality of independent display lists, said at least first high priority and second low priority independent FIFO buffers interfacing with said at least one stored program computer; FIFO controller means coupled to said at least first high priority and second low priority independent FIFO buffers; and a graphics processor coupled to each of said at least first high priority and second low priority independent FIFO buffers for generating graphic pixel signals in response to said independent display lists received from any of said at least first high priority and second low priority independent FIFO buffers; said FIFO controller means comprising means for allowing said at least one stored program computer to utilize said at least first high priority and second low priority independent FIFO buffers and providing real-time, high speed context switching such that a first of said independent display lists having a higher priority will interrupt processing in the graphics processor of a second independent display list having a lower priority, upon said interruption said graphics processor processes said first independent display list having a higher priority, and upon the graphics processor completing processing of said first display list, the context of said second independent display list is restored to said graphics processor and said graphics processor resumes processing said second independent display list.