US4172284A — Priority interrupt apparatus employing a plural s…

Claim 1

Independent Claim 222 words

A priority interrupt unit for use in a data processing system having different stored interrupt routines for different interrupt sources and comprising: input circuitry for successively supplying plural-bit interrupt requests each having a priority level field and an interrupt source identifying field; a plural stage shift register, each stage having enough bit positions to hold at least the priority level and source identifying fields of a single interrupt request and successive stages being assigned to successively lower priority levels, the highest priority level stage being coupled to the input circuitry for initially receiving each incoming interrupt request; a plurality of interrupt mechanisms individually associated with different ones of the shift register stages and responsive to interrupt source identifying fields transferred to such mechanisms for developing appropriate interrupt routine address pointers for the data processing system; and transfer circuitry responsive to the contents of the shift register stages for transferring an interrupt request in any given shift register stage to the next shift register stage if the request priority level field does not match the priority level assigned to the given shift register stage and for transferring the interrupt source identifying field of such interrupt request to the interrupt mechanism associated with the given shift register stage if the request priority level field does match the priority level assigned to the given stage.

Claim 2

Dependent Claim 222 words

A priority interrupt unit for use in a data processing system having different stored interrupt routines for different interrupt sources and comprising: input circuitry for successively supplying plural-bit interrupt requests each having a priority level field and an interrupt source identifying field; a plural stage shift register, each stage having enough bit positions to hold at least the priority level and source identifying fields of a single interrupt request and successive stages being assigned to successively lower priority levels, the highest priority level stage being coupled to the input circuitry for initially receiving each incoming interrupt request; a plurality of interrupt mechanisms individually associated with different ones of the shift register stages and responsive to interrupt source identifying fields transferred to such mechanisms for developing appropriate interrupt routine address pointers for the data processing system; and transfer circuitry responsive to the contents of the shift register stages for transferring an interrupt request in any given shift register stage to the next shift register stage if the request priority level field does not match the priority level assigned to the given shift register stage and for transferring the interrupt source identifying field of such interrupt request to the interrupt mechanism associated with the given shift register stage if the request priority level field does match the priority level assigned to the given stage.

Claim 3

Dependent Claim 128 words

A priority interrupt unit in accordance with claim 1 wherein each interrupt mechanism includes: a storage stack for receiving and storing the interrupt source identifying fields of those interrupt requests having the same priority level as the shift register stage with which the interrupt mechanism is associated; interrupt routine address circuitry for receiving an interrupt source identifying field and developing in response thereto the appropriate interrupt routine address pointer; and circuitry response to the presence of interrupt source identifying fields in the storage stack for transferring one interrupt source identifying field at a time from the storage stack to the interrupt routine address circuitry and for transferring such source identifying fields to the address circuitry in the same order in which they are received by the storage stack.

Claim 4

Dependent Claim 272 words

A priority level controlled unit for handling interrupt requests of interrupt sources having different interrupt priority levels comprising: input circuitry for supplying interrupt requests each having a priority level field and a priority sublevel field; a shift register whose stages are assigned to different ones of the interrupt priority levels, the first stage in such shift register being coupled to the input circuitry for initially receiving each incoming interrupt request; a comparator mechanism associated with each shift register stage for comparing the priority level field of an interrupt request residing in such stage with the priority level value assigned to such stage for indicating the existence of priority level matches and mismatches; a transfer mechanism for transferring an interrupt request in any given shift register stage to the next shift register stage when the comparator mechanism associated with the given stage indicates a priority level mismatch; a storage stack associated with each shift register stage for storing the priority sublevel field contained in an interrupt request in its shift register stage when the comparator mechanism associated with its shift register stage indicates a priority level match; a base address register associated with each shift register stage for storing a base address initially loaded into such register by the data processing system with which the priority unit is used; and instruction address circuitry associated with each shift register stage for combining the base address with the earliest received unprocessed priority sublevel field then pending in the associated storage stack to form an instruction address pointer for the first instruction of an interrupt routine for executing the interrupt request of the corresponding interrupt source.

Claim 5

Dependent Claim 272 words

A priority level controlled unit for handling interrupt requests of interrupt sources having different interrupt priority levels comprising: input circuitry for supplying interrupt requests each having a priority level field and a priority sublevel field; a shift register whose stages are assigned to different ones of the interrupt priority levels, the first stage in such shift register being coupled to the input circuitry for initially receiving each incoming interrupt request; a comparator mechanism associated with each shift register stage for comparing the priority level field of an interrupt request residing in such stage with the priority level value assigned to such stage for indicating the existence of priority level matches and mismatches; a transfer mechanism for transferring an interrupt request in any given shift register stage to the next shift register stage when the comparator mechanism associated with the given stage indicates a priority level mismatch; a storage stack associated with each shift register stage for storing the priority sublevel field contained in an interrupt request in its shift register stage when the comparator mechanism associated with its shift register stage indicates a priority level match; a base address register associated with each shift register stage for storing a base address initially loaded into such register by the data processing system with which the priority unit is used; and instruction address circuitry associated with each shift register stage for combining the base address with the earliest received unprocessed priority sublevel field then pending in the associated storage stack to form an instruction address pointer for the first instruction of an interrupt routine for executing the interrupt request of the corresponding interrupt source.

Claim 6

Dependent Claim 57 words

A priority level controlled unit in accordance with claim 3 wherein each comparator mechanism also includes circuitry responsive to the condition of the storage stack associated with its shift register stage for determining whether such storage stack is full and for preventing transfer of a further priority sublevel field to such storage stack if it is full.

Claim 7

Dependent Claim 77 words

A priority level controlled unit in accordance with claim 3 wherein each comparator mechanism includes a comparator circuit and a mask register containing a coded representation of the associated interrupt priority level, the comparator circuit being connected on the one hand to the priority level field portion of the associated shift register stage and on the other hand to the mask register for comparing their contents and generating the appropriate one of the match and mismatch indications.

Claim 8

Dependent Claim 60 words

A priority level controlled unit in accordance with claim 3 wherein a test mechanism is associated with each storage stack for testing the stack status for determining whether any unprocessed priority sublevel fields are pending therein and for enabling transfer of the oldest such priority sublevel field to the instruction address circuitry when the result of the testing is positive.

Claim 9

Dependent Claim 79 words

A priority level controlled unit in accordance with claim 6 wherein each test mechanism includes a comparator circuit and a mask register containing a coded representation for the case where the storage stack is not empty, the comparator circuit being connected on the one hand to the output stage of the storage stack and on the other hand to the mask register for comparing their status and generating a transfer enabling signal when the storage stack is not empty.

Claim 10

Dependent Claim 244 words

A priority level controlled unit in accordance with claim 3 and including: a first gating mechanism for transferring a priority sublevel field from a shift register stage to its associated storage stack if the associated comparator mechanism has determined that the priority level of the interrupt request and that of the shift register stage match and that the storage stack is not full; a second gating mechanism for transferring the priority sublevel field contained in the current output of a storage stack to the associated instruction address circuitry if the storage stack is not empty; a third gating mechanism for transferring the base address stored in a base address register to the associated instruction address circuitry if a priority sublevel field is also transferred to the same instruction address circuitry; a fourth gating mechanism for transferring an interrupt request stored in any given shift register stage to the shift register stage associated with the next lower interrupt priority level if the comparator mechanism associated with the given shift register stage indicates a priority level mismatch and such next shift register stage is not occupied by another interrupt request; and a fifth gating mechanism for transferring an instruction address pointer pending in an instruction address circuitry to a data processor control store storing the various interrupt routines if no blockage of such transfer is caused by the presence of a pending instruction address pointer in an instruction address circuitry for a higher interrupt priority level.

Claim 11

Independent Claim 310 words

A method for handling interrupt requests of interrupt sources having different interrupt priority levels comprising: transferring one interrupt request at a time to a first register, each such request being transferred thereto only if the first register is free of the previous request transferred thereto; determining whether an interrupt request pending in the first register is of a first priority level; transferring an interrupt request pending in the first register to a first interrupt mechanism if such request is of the first priority level and if the first interrupt mechanism is not full; enabling the first interrupt mechanism to initiate execution of an appropriate interrupt routine if an interrupt request is pending therein; transferring an interrupt request pending in the first register to a second register if such request is not of the first priority level and if the second register is free; determining whether an interrupt request pending in the second register is of a second priority level; transferring an interrupt request pending in the second register to a second interrupt mechanism if such request is of the second priority level and if the second interrupt mechanism is not full; enabling the second interrupt mechanism to initiate execution of an appropriate interrupt routine if an interrupt request is pending therein and no interrupt request is pending in the first interrupt mechanism; transferring an interrupt request pending in the second register to a third register if such request is not of the second priority level and if the third register is free; transferring an interrupt request pending in the third register to a third interrupt mechanism if the third interrupt mechanism is not full; and enabling the third interrupt mechanism to initiate execution of an appropriate interrupt routine if an interrupt request is pending therein and no interrupt request is pending in either the first or the second interrupt mechanism.

Claim 12

Independent Claim 310 words

A method for handling interrupt requests of interrupt sources having different interrupt priority levels comprising: transferring one interrupt request at a time to a first register, each such request being transferred thereto only if the first register is free of the previous request transferred thereto; determining whether an interrupt request pending in the first register is of a first priority level; transferring an interrupt request pending in the first register to a first interrupt mechanism if such request is of the first priority level and if the first interrupt mechanism is not full; enabling the first interrupt mechanism to initiate execution of an appropriate interrupt routine if an interrupt request is pending therein; transferring an interrupt request pending in the first register to a second register if such request is not of the first priority level and if the second register is free; determining whether an interrupt request pending in the second register is of a second priority level; transferring an interrupt request pending in the second register to a second interrupt mechanism if such request is of the second priority level and if the second interrupt mechanism is not full; enabling the second interrupt mechanism to initiate execution of an appropriate interrupt routine if an interrupt request is pending therein and no interrupt request is pending in the first interrupt mechanism; transferring an interrupt request pending in the second register to a third register if such request is not of the second priority level and if the third register is free; transferring an interrupt request pending in the third register to a third interrupt mechanism if the third interrupt mechanism is not full; and enabling the third interrupt mechanism to initiate execution of an appropriate interrupt routine if an interrupt request is pending therein and no interrupt request is pending in either the first or the second interrupt mechanism.

Claim 13

Dependent Claim 104 words

A method for handling interrupt requests in accordance with claim 9 wherein: each of the first, second and third interrupt mechanisms includes a storage stack for storing a number of interrupt requests; the interrupt requests transferred to any given interrupt mechanism are stored in its storage stack in the same order in which they are received; and each interrupt mechanism is operated to initiate execution of the interrupt routines for the different interrupt requests in the same order in which such requests were transferred to its storage stack so that the interrupt requests in any given storage stack are honored in a first-in-first-out manner.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1982-10-22	1983-04-23	1983-10-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1986-10-22	1987-04-23	1987-10-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1990-10-22	1991-04-23	1991-10-23	$7700.00	Window Closed / Lapsed

Priority interrupt apparatus employing a plural stage shift register having separate interrupt mechanisms coupled to the different stages thereof for segregating interrupt requests according to priority levels

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