Output buffer circuit for a low voltage EPROM

Claim 2

An output buffer circuit for a low voltage device for allowing for high speed performance while also minimizing noise, the circuit comprising: a pull-up transistor for providing a drive potential to an output; a pull-down transistor for providing a drive potential to the output; means for receiving a logic signal, the logic signal providing an indication that the output buffer circuit is to be operated at a high voltage; and means coupled between the receiving means and the pull-up and pull-down transistors for reducing the turn-on speed of the pull-up and pull-down transistors when the logic signal is detected, whereby the output buffer circuit operates at a high speed when the logic signal is not present, indicating that the output buffer circuit is to be operating at a low voltage and at a slower speed when the logic signal is present.

Claim 3

The output buffer circuit of claim 1 in which the reducing means comprises: a first strong transistor coupled to the logic signal and to the pull-up transistor; a first weak transistor coupled to the first strong transistor and to the pull-up transistor; an inverter coupled to the logic signal; a second strong transistor coupled to the inverter and the pull-down transistor; and a second weak transistor coupled to the second strong transistor and the pull-down transistor.

Claim 4

The output buffer circuit of claim 2 in which the pull-up transistor, first weak transistor and second strong transistor are p-channel devices.

Claim 5

The output buffer circuit of claim 3 in which the pull-down transistor, first strong transistor and second weak transistor are n-channel devices.

Claim 6

The output buffer circuit of claim 4 in which the logic signal disables the first and second strong transistors when the logic signal is active.

Claim 7

The output buffer circuit of claim 1 in which the logic signal is a programming verify signal.

Claim 8

The output buffer circuit of claim 5 in which the first weak transistor is connected as a diode.

Claim 9

The output buffer circuit of claim 6 in which the second weak transistor is connected as a diode.

Claim 10

The output buffer circuit of claim 8 in which the first and second weak transistors turn on the pull-up and pull-down transistors slowly and weakly where the logic signal is present.

Claim 11

The output buffer circuit of claim 1 in which the low voltage is in the range of 2.7-3.6 volts.

Claim 12

The output buffer circuit of claim 6 in which the programming verify signal provides the high voltage is 6 volts or greater.

Claim 13

In combination with an output buffer circuit, the output buffer circuit comprising a pull-up transistor and a pull-down transistor, the output buffer circuit providing an output voltage responsive to an input signal; the output buffer circuit operating efficiently at a low voltage range; a circuit for allowing for high speed performance while minimizing noise comprising; means for receiving a logic signal, the logic signal providing an indication that the output buffer circuit is to be operated at high voltage; and means coupled to the detecting means for reducing the speed of the output buffer circuit by reducing the charge rate on the pull-up transistor and pull-down transistor responsive to the detection of the logic signal.

Claim 14

In combination with an output buffer circuit, the output buffer circuit comprising a pull-up transistor and a pull-down transistor, the output buffer circuit providing an output voltage responsive to an input signal; the output buffer circuit operating efficiently at a low voltage range; a circuit for allowing for high speed performance while minimizing noise comprising; means for receiving a logic signal, the logic signal providing an indication that the output buffer circuit is to be operated at high voltage; and means coupled to the detecting means for reducing the speed of the output buffer circuit by reducing the charge rate on the pull-up transistor and pull-down transistor responsive to the detection of the logic signal.

Claim 15

The output buffer circuit of claim 12 in which the reducing means comprises: a first strong transistor coupled to the receiving means and to the pull-up transistor; a first weak transistor coupled to the first strong transistor and to the pull-up transistor; an inverter coupled to the logic signal; a second strong transistor coupled to the inverter and the pull-down transistor; and a second weak transistor coupled to the second strong transistor and the pull-down transistor.

Claim 16

The output buffer circuit of claim 13 in which the pull-up transistor, the first weak transistor and the second strong transistor are p-channel devices.

Claim 17

The output buffer circuit of claim 14 in which the pull-down transistor, the first strong transistor and the second weak transistor are n-channel devices.

Claim 18

The output buffer circuit of claim 15 in which the logic signal disables the first and second strong transistors when the logic signal is detected.

Claim 19

The output buffer circuit of claim 12 in which the logic signal is a programming verify signal.

Claim 20

The output buffer circuit of claim 16 in which the first weak transistor is connected as a diode.

Claim 21

The output buffer circuit of claim 17 in which the second weak transistor is connected as a diode.

Claim 22

The output buffer circuit of claim 19 in which the first and second weak transistors turn on the pull-up and pull-down transistors slowly and weakly when the logic signal is detected.

Claim 23

The output buffer circuit of claim 12 in which the low voltage range is 2.7-3.6 volts.

Claim 24

The output buffer circuit of claim 12 in which the high voltage is 6 volts or greater.

Claim 25

An output buffer circuit for a low voltage EPROM device, comprising: a p-channel pull-up transistor for providing a drive potential to an output; a n-channel pull-down transistor for providing a drive potential to the output; means for receiving a programming verify logic signal, first means coupled between the detecting means and the pull-up transistor for turning the pull-up transistor on slowly and weakly responsive to the logic signal being active, the first means includes a strong- n-channel transistor coupled to the detecting means and a p-channel weak transistor coupled to the strong n-channel transistor and to the pull-up transistor, the first weak transistor being connected as a diode; and second means coupled between the receiving means and the pull-down transistor for turning the pull-down transistor on slowly and weakly responsive to the logic signal being active, the second means includes a second strong p-channel transistor coupled to the detecting means and a weak n-channel transistor coupled to the strong p-channel transistor and to the pull-down transistor, the weak n-channel transistor being connected as a diode.

Claim 26

An output buffer circuit for a low voltage EPROM device, comprising: a p-channel pull-up transistor for providing a drive potential to an output; a n-channel pull-down transistor for providing a drive potential to the output; means for receiving a programming verify logic signal, first means coupled between the detecting means and the pull-up transistor for turning the pull-up transistor on slowly and weakly responsive to the logic signal being active, the first means includes a strong- n-channel transistor coupled to the detecting means and a p-channel weak transistor coupled to the strong n-channel transistor and to the pull-up transistor, the first weak transistor being connected as a diode; and second means coupled between the receiving means and the pull-down transistor for turning the pull-down transistor on slowly and weakly responsive to the logic signal being active, the second means includes a second strong p-channel transistor coupled to the detecting means and a weak n-channel transistor coupled to the strong p-channel transistor and to the pull-down transistor, the weak n-channel transistor being connected as a diode.