US4975599A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and resulting devices for compensating for process variables in a CMOS device driver circuit
Assignee: International Business Machines Corp
•
Filing: 1989-07-26
•
Granted: 1990-12-04
•
Expires: 2009-07-26
Abstract
Abstract According to the present invention, an improved CMOS integrated circuit and an improved method of forming the circuit is provided. The circuit has a first FET device and a second FET device, and at least one performance characteristic of said first and second FET devices varies in the same manner with the variation of at least one performance related process variable condition. Each of said FET devices has an output signal at least one characteristic of which is changed by a change in the performance related variable condition. The first and second FET devices are connected such that the one output characteristic of the second FET device acts in opposition to the one output characteristic of the first FET device to provide a merged output signal representative of the combined effect of the two FET devices. The second FET device is constructed so as to be more responsive to the variations in said performance related variable condition than the first FET device and to have a weaker output signal than the first FET device, whereby the merged output signal of the two FET devices is maintained relatively constant irrespective of variations in the performance related variable condition.
Inventors
- 👤 John G. Petrovick, Jr.
- 👤 Robert S. Taylor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:36
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/6871; H03K17/6872; H03K17/14; H03K17/145; H03K19/00; H03K19/003; H03K19/00369; H03K19/00384
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
165 words
An integrated circuit comprising at least a first FET device and a second FET device, and wherein a given performance characteristic of each of said first and second FET devices varies in the same manner with variation of at least one performance related variable condition, each of said FET devices have an output signal at least one characteristic of which is changed by a change in said performance related variable condition, the output signals of said first and second FET devices being merged, wherein said one output characteristic of said second FET device acts in opposition to said one output of said first FET device; said second FET device being constructed to be more responsive to said variations in said performance related variable condition than said first FET device and being constructed to have a weaker output signal than said first FET device whereby the merged output signal at said FET devices is maintained relatively constant irrespective of variations in the performance related variables condition.
Claim 2
Dependent Claim
165 words
An integrated circuit comprising at least a first FET device and a second FET device, and wherein a given performance characteristic of each of said first and second FET devices varies in the same manner with variation of at least one performance related variable condition, each of said FET devices have an output signal at least one characteristic of which is changed by a change in said performance related variable condition, the output signals of said first and second FET devices being merged, wherein said one output characteristic of said second FET device acts in opposition to said one output of said first FET device; said second FET device being constructed to be more responsive to said variations in said performance related variable condition than said first FET device and being constructed to have a weaker output signal than said first FET device whereby the merged output signal at said FET devices is maintained relatively constant irrespective of variations in the performance related variables condition.
Claim 3
Dependent Claim
41 words
The invention as defined in claim 1 wherein said circuit is a drive circuit and includes a third FET device the gate of which is connected to and operable by the merged output signal of said first and second FET devices.
Claim 4
Dependent Claim
29 words
The invention as defined in claim 2 wherein said circuit is formed on an integrated circuit chip, and the third FET device controls the operation of a capacitive load.
Claim 5
Dependent Claim
16 words
The invention as defined in claim 1 wherein said performance related process variable is channel length.
Claim 6
Dependent Claim
15 words
The invention as defined in claim 1 wherein said process related variable is channel width.
Claim 7
Dependent Claim
15 words
The invention as defined in claim 1 wherein said process related variable is threshold voltage.
Claim 8
Dependent Claim
15 words
The invention as defined in claim 1 wherein the process related variable is base mobility.
Claim 9
Dependent Claim
16 words
The invention as defined in claim 1 wherein the process variable compensates for power supply tolerance.
Claim 10
Dependent Claim
17 words
The invention as defined in claim 1 wherein the process variable compensates for device operating on temperatures.
Claim 11
Independent Claim
168 words
A method of forming an integrated circuit having at least a first FET device and second FET device, and wherein a given performance characteristic of said first and second FET devices varies in the same manner with the variation of at least one performance related variable condition, and wherein each FET device has an output signal at least one characteristic of which is changed by a change in said performance related variable condition, the improvement which comprises, merging the output signals of said first and second FET devices wherein said one output characteristic of said second FET device acts in opposition to said one output characteristic of said first FET devices, constructing said second FET device to be more responsive to said variations in said performance related variable condition than said first FET device and to have a weaker output signal than said first FET device, whereby the merged output signal of said FET devices is maintained relatively constant irrespective of variations in the performance related variable conditions.
Claim 12
Independent Claim
168 words
A method of forming an integrated circuit having at least a first FET device and second FET device, and wherein a given performance characteristic of said first and second FET devices varies in the same manner with the variation of at least one performance related variable condition, and wherein each FET device has an output signal at least one characteristic of which is changed by a change in said performance related variable condition, the improvement which comprises, merging the output signals of said first and second FET devices wherein said one output characteristic of said second FET device acts in opposition to said one output characteristic of said first FET devices, constructing said second FET device to be more responsive to said variations in said performance related variable condition than said first FET device and to have a weaker output signal than said first FET device, whereby the merged output signal of said FET devices is maintained relatively constant irrespective of variations in the performance related variable conditions.
Claim 13
Dependent Claim
35 words
The invention as defined in claim 10 wherein a third FET device is provided, the gate of which is connected to and operable by the merged output signal of said first and second FET devices.
Claim 14
Dependent Claim
29 words
The invention as defined in claim 11 wherein said circuit is formed on a interated circuit chip, and the third FET device controls the operation of a capacitive load.
Claim 15
Dependent Claim
16 words
The invention as defined in claim 10 wherein said performance related process variable is channel length.
Claim 16
Dependent Claim
15 words
The invention as defined in claim 10 wherein said process related variable is channel width.
Claim 17
Dependent Claim
15 words
The invention as defined in claim 10 wherein said process related variable is threshold voltage.
Claim 18
Dependent Claim
15 words
The invention as defined in claim 10 where the process related variable is base mobility.
Claim 19
Dependent Claim
16 words
The invention as defined in claim 10 wherein the process variable compensates for power supply tolerance.
Claim 20
Dependent Claim
16 words
The invention as defined in claim 10 wherein the process variable compensates for device operating temperature.
References Cited (Backward Citations)
US4242604A
Cited
US4473762A
Cited
US4614882A
Cited
US4742247A
Cited
US4760288A
Cited
US4791326A
Cited
US4763021A
Cited
US4818901A
Cited
US4894561A
Cited
US4820942A
Cited
US4857770A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-03 | 1994-06-04 | 1994-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-03 | 1998-06-04 | 1998-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-03 | 2002-06-04 | 2002-12-04 | $7700.00 | Window Closed / Lapsed |