Low cost, thermally efficient, and surface mountable semiconductor package for a high applied power VLSI die

Claim 1

A semiconductor package comprising: a) a VLSI semiconductor die having a plurality of electrical bond pads, an active side, an inactive side, and electrical power W applied to it during operation; b) a substrate having a housing cavity, at least one wiring plane, and a plurality of electrical contacts, for accommodating said VLSI die and electrically connecting said VLSI die to a PWB, said housing cavity being disposed at a center of said substrate having a top surface opening, an underside opening, and a plurality of steps, at least one of said steps exposing at least partially said at least one wiring plane, said VLSI die being accommodated at said top surface opening of said stepped housing cavity, wire bonded to said at least partially exposed at least one wiring plane, and sealed with a sealant material, said electrical contacts being suitable for surface mounting said semiconductor package onto said PWB; c) a heat slug having a ring of support surface area and an access cavity for supporting said VLSI die at said top surface opening of said stepped housing cavity and providing access to said inactive side of said VLSI die, said ring of support surface area of said heat slug, said top surface opening of said stepped housing cavity of said substrate, and said VLSI die being coordinated in sizes; d) a heat sink having a stem for accessing and contacting said inactive side of said VLSI die through said access cavity of said heat slug and removing heat generated by said VLSI die during operation, said heat sink being made of a thermally conductive material having a thermal conductivity of K, said VLSI die, said top surface opening of said stepped housing cavity of said substrate, said access cavity, and said stem being coordinated in sizes, allowing said stem to contact sufficient surface area of said inactive side of said VLSI die in view of said W and said K to remove heat at a sufficient dissipation rate to keep temperature in said stepped housing cavity of said substrate from rising above an unacceptable threshold during operation.