US5359549A
Expired / Lapsed
US
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Orthogonal transformation processor for compressing information
Assignee: Ricoh Co Ltd
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Filing: 1993-05-05
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Granted: 1994-10-25
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Expires: 2013-05-05
Abstract
Abstract An orthogonal transformation processor has a first one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation; a memory device for temporarily storing an output of the first one-dimensional orthogonal transformation calculator; a second one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation and inputting an output of the memory device thereto; and an address generator for designating an address of the memory device and replacing row and column addresses with each other in accordance with a switching operation of writing and reading operations of the memory device. Instead of this address generator, the orthogonal transformation processor may have an address generator for designating an address of the memory device and replacing row and column addresses with each other i n accordance with calculating operations of the first and second one-dimensional orthogonal transformation calculators. The orthogonal transformation processor may further have a reading-writing control section for reading one data of the memory device and writing new results calculated by the first one-dimensional orthogonal transformation calculator to the same address after the data reading operation.
Inventors
- 👤 Masafumi Tanaka
- 👤 Kazuo Sakamoto
- 👤 Tatsuya Fujii
- 👤 Ryo Fukui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:30
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/14; G06F17/147
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
122 words
An orthogonal transformation processor comprising: a first one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation; a memory device for temporarily storing an output of the first one-dimensional orthogonal transformation calculator; a second one-dimensional orthogonal transformation calculator for receiving an output of said memory device thereto, and calculating a one-dimensional orthogonal transformation; and an address generator for designating an address of said memory device and replacing row and column addresses with each other in synchronization with a switching of writing and reading operations of said memory device, said address generator comprising a first counter, a second counter and a switching circuit for switching so as to selectively combine an output of said first counter with an output of said second counter.
Claim 2
Dependent Claim
122 words
An orthogonal transformation processor comprising: a first one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation; a memory device for temporarily storing an output of the first one-dimensional orthogonal transformation calculator; a second one-dimensional orthogonal transformation calculator for receiving an output of said memory device thereto, and calculating a one-dimensional orthogonal transformation; and an address generator for designating an address of said memory device and replacing row and column addresses with each other in synchronization with a switching of writing and reading operations of said memory device, said address generator comprising a first counter, a second counter and a switching circuit for switching so as to selectively combine an output of said first counter with an output of said second counter.
Claim 3
Dependent Claim
55 words
An orthogonal transformation processor according to claim 1, wherein said processor further comprises a reading-writing control section for transferring a signal representing the switching of writing and reading operations of said memory device to said address generator, and said address generator replaces said row and column addresses with each other in response to said signal.
Claim 4
Dependent Claim
21 words
An orthogonal transformation processor according to claim 1, wherein said address generator exchanges upper bits with lower bits of an address.
Claim 5
Dependent Claim
54 words
An orthogonal transformation processor according to claim 3, wherein said processor further comprises a reading-writing control section for transferring a signal representing the switching of writing and reading operations of said memory device to said address generator, and said address generator replaces row and column addresses with each other in response to said signal.
Claim 6
Dependent Claim
166 words
An orthogonal transformation processor comprising: a first one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation; a memory device for temporarily storing an output of the first one-dimensional orthogonal transformation calculator; a second one-dimensional orthogonal transformation calculator for receiving an output of said memory device thereto, and calculating a one-dimensional orthogonal transformation; an address generator for generating an address, said address generator being adapted to replace row and column addresses with each other in accordance with calculating operations of said first and second one-dimensional orthogonal transformation calculators; an address decoder for receiving the address from the address generator and designating an address of the memory device; and a reading-writing control section for controlling said memory device in such a manner that a result calculated by one of said first and second one-dimensional orthogonal transformation calculators is written to the same address as data, just after one data of said memory device is read to the other of said first and second one-dimensional orthogonal transformation calculators.
Claim 7
Dependent Claim
166 words
An orthogonal transformation processor comprising: a first one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation; a memory device for temporarily storing an output of the first one-dimensional orthogonal transformation calculator; a second one-dimensional orthogonal transformation calculator for receiving an output of said memory device thereto, and calculating a one-dimensional orthogonal transformation; an address generator for generating an address, said address generator being adapted to replace row and column addresses with each other in accordance with calculating operations of said first and second one-dimensional orthogonal transformation calculators; an address decoder for receiving the address from the address generator and designating an address of the memory device; and a reading-writing control section for controlling said memory device in such a manner that a result calculated by one of said first and second one-dimensional orthogonal transformation calculators is written to the same address as data, just after one data of said memory device is read to the other of said first and second one-dimensional orthogonal transformation calculators.
Claim 8
Dependent Claim
69 words
An orthogonal transformation processor according to claim 5, wherein said address generator comprises a first counter, a second counter and a switching circuit for switching so as to selectively combine an output of said first counter with an output of said second counter, and is adapted to replace row and column addresses with each other in synchronization with a switching of writing and reading operations of said memory device.
Claim 9
Dependent Claim
50 words
An orthogonal transformation processor according to claim 5, wherein said reading-writing control section transfers a signal representing a switching of writing and reading operations of said memory device to said address generator, and said address generator replaces said row and column addresses with each other in response to said signal.
Claim 10
Dependent Claim
53 words
An orthogonal transformation processor according to claim 5, wherein said address generator comprises a first counter, a second counter and a switching circuit for switching so as to selectively combine an output of said first counter with an output of said second counter for exchanging upper bits with lower bits of the address.
Claim 11
Dependent Claim
36 words
An orthogonal transformation processor according to claim 8, said address generator is adapted to replace row and column addresses with each other in synchronization with a switching of writing and reading operations of said memory device.
Claim 12
Dependent Claim
49 words
An orthogonal transformation processor according to claim 8, wherein said reading-writing control section transfers a signal representing a switching of writing and reading operations of said memory device to said address generator, and said address generator replaces row and column addresses with each other in response to said signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-24 | 1998-04-25 | 1998-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-24 | 2002-04-25 | 2002-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-24 | 2006-04-25 | 2006-10-25 | $7700.00 | Window Closed / Lapsed |