High speed cosine transform

Claim 2

A circuit for developing a plurality of transform coefficient signals comprising: a plurality of multipliers, each capable of multiplying by one of at most two fixed constants, responsive to sequences of applied input signals, for developing sequences of product signals; means for reversing the sign of said product signals in accordance with a predetermined sequence for each of said multipliers; and a plurality of cyclical pipelined accumulator means responsive to said means for reversing, each capable of applying its output signal to its input and developing different ones of said transform coefficient signals.

Claim 3

The circuit of claim 1, further comprising input signal reordering means interposed between said sequences of said applied input signals and said plurality of constant multipliers.

Claim 4

The circuit of claim 1 further comprising output signal reordering means responsive to said transform coefficient signals.

Claim 5

The circuit of claim 1, further including means responsive to said transform coefficient signals for receiving said transform coefficient in parallel and providing said transform coefficient signals serially at an output port of said transform circuit.

Claim 6

The circuit of claim 4 further comprising output signal reordering means responsive to said transform coefficient signals serially appearing at said output port of said transform circuit.

Claim 7

The circuit of claim 5, further comprising input signal reordering means interposed between said sequences of said applied input signals and said plurality of constant multipliers.

Claim 8

The transform circuit of claim 1 wherein each of said cyclical pipeline accumulators comprises: a plurality of combine-and-store networks, each having two inputs and one output, for arithmetically combining signals at said two inputs, storing the combined signals and making the stored signals available at said one output, with said combine-and-store networks connected in a ring, where one of said inputs of each of said combine-and-store networks is connected to said output of another one of said combine-and-store networks, and said second input of each of said combine-and-store networks is responsive to said product signals.

Claim 9

A transform circuit for developing a set of transform signals from a sequence of applied input signals comprising: a plurality of multipliers responsive to said input signals, each multiplying said input signals by one of at most two different preselected constants and developing thereby a plurality of product signals; and cyclical pipeline accumulator means responsive to said plurality of product signal including means for applying its output signal to its input, for adding to or subtracting from a developing set of transform signals of said input signals, with said adding to or subtracting from said developing set of transform signals being controlled in accordance with a preselected sequence, and said developing set of transform signals becoming said set of transform signals upon completion of said adding or subtracting.

Claim 10

A transform circuit for developing a set of transform signals from a sequence of applied input signals comprising: a plurality of multipliers responsive to said input signals, each multiplying said input signals by one of at most two different preselected constants and developing thereby a plurality of product signals; and cyclical pipeline accumulator means responsive to said plurality of product signal including means for applying its output signal to its input, for adding to or subtracting from a developing set of transform signals of said input signals, with said adding to or subtracting from said developing set of transform signals being controlled in accordance with a preselected sequence, and said developing set of transform signals becoming said set of transform signals upon completion of said adding or subtracting.

Claim 11

The transform circuit of claim 8 wherein said cyclical pipeline accumulator means comprises: a plurality of combine-and-store networks, each having two inputs and one output, for arithmetically combining signals at said two inputs, storing the combined signals and making the stored signals available at said one output, with said combine-and-store networks connected in a ring, where one of said inputs of each of said combine-and-store networks is connected to said output of another one of said combine-and-store networks, and said second input of each of said combine-and-store networks is responsive to said product signals.

Claim 12

A circuit for developing a 2 i point transform from 2 i input samples where i is an integer comprising: 2 i -1 multipliers, each responsive to said 2 i input samples and each multiplying said input samples by a fixed constant to develop product signals; means for reversing the sign of said product signals in accordance with a predetermined sequence for each of said multipliers; and each of said cyclical pipelined means being capable of applying its output signal to its input, a plurality of cyclical pipeline accumulator means responsive to said means for reversing, for developing 2 i transform coefficient signals.

Claim 13

A circuit for developing a 2 i point transform from 2 i input samples where i is an integer comprising: 2 i -1 multipliers, each responsive to said 2 i input samples and each multiplying said input samples by a fixed constant to develop product signals; means for reversing the sign of said product signals in accordance with a predetermined sequence for each of said multipliers; and each of said cyclical pipelined means being capable of applying its output signal to its input, a plurality of cyclical pipeline accumulator means responsive to said means for reversing, for developing 2 i transform coefficient signals.

Claim 14

The circuit of claim 10 wherein said transform is a cosine transform and said constants are cosine values of the angles comprising the multiples of π/(4 2 i ).

Claim 15

The circuit of claim 10 wherein said plurality of cyclical pipeline accumulator means includes a pipelined arrangement of 2 i-1 two input adders supplying signals to one register in a set of 2 i-1 registers, with one input of each of said adders being responsive to said product signals and the other input of each of said adders being responsive to a different register from said set of registers.

Claim 16

A two dimensional transform generator comprising: a first one-dimensional transform generator responsive to input signals including a first plurality of multipliers, each capable of multiplying by one of at most two fixed constants, for developing sequences of first product signals; first means for reversing the sign of said product signals in accordance with a predetermined sequence for each of said multipliers in said first plurality of multipliers; and a first plurality of cyclical pipeline accumulator means each of said cyclical pipelined accumulator means being capable of applying its output signal to its input, responsive to said first means for reversing, for developing intermediate coefficient signals, an intermediate reordering memory responsive to said intermediate coefficient signals; and a second one-dimensional transform generator including a second plurality of constant multipliers, connected to said intermediate reordering memory, for developing sequences of second product signals; second means for reversing the sign of said second product signals in accordance with a predetermined sequence for each of said multipliers in said second plurality of multipliers; and a second plurality of cyclical pipeline accumulator means each of said cyclical pipeline accumulator means being capable of applying its output signal to its input, responsive to said second means for reversing, for developing final coefficient signals.

Claim 17

A two dimensional transform generator comprising: a first one-dimensional transform generator responsive to input signals including a first plurality of multipliers, each capable of multiplying by one of at most two fixed constants, for developing sequences of first product signals; first means for reversing the sign of said product signals in accordance with a predetermined sequence for each of said multipliers in said first plurality of multipliers; and a first plurality of cyclical pipeline accumulator means each of said cyclical pipelined accumulator means being capable of applying its output signal to its input, responsive to said first means for reversing, for developing intermediate coefficient signals, an intermediate reordering memory responsive to said intermediate coefficient signals; and a second one-dimensional transform generator including a second plurality of constant multipliers, connected to said intermediate reordering memory, for developing sequences of second product signals; second means for reversing the sign of said second product signals in accordance with a predetermined sequence for each of said multipliers in said second plurality of multipliers; and a second plurality of cyclical pipeline accumulator means each of said cyclical pipeline accumulator means being capable of applying its output signal to its input, responsive to said second means for reversing, for developing final coefficient signals.

Claim 18

The two dimensional transform generator of claim 13 further comprising a preprocessing reordering memory interposed between said inputs signals and said first one-dimensional transform generator.

Claim 19

The two dimensional transform generator of claim 13 further comprising a postprocessing reordering memory responsive to said final coefficient signals.

Claim 20

The apparatus of claim 14, further comprising: means for applying image samples to said preprocessing reordering memory to develop discrete cosine transform coefficients at said final set of coefficient signals, and means for compressing said final set of coefficient signals.

Claim 21

The apparatus of claim 15, further comprising means for applying discrete cosine transform signals to said first one-dimensional transform generator to develop image samples at said final set of coefficient signals.