An orthogonal transform processor

Claim 2

An orthogonal transform processor comprising: a rotator responsive to a first rotator input signal, x₀, a second rotator input signal, x₁, a first coefficient signal, c₀, and a second coefficient signal, c₁, for developing a first rotator output signal equal to c₀x₀ + c₁x₁ and a second rotator output signal equal to -c₁x₀ + c₀x₁; a communication circuit, responsive to applied processor input signals, for applying to said rotator said first and second rotator input signals, for accepting said first and said second rotator output signals, and for delivering transformed output signals of said orthogonal transform processor; and means, responsive to an initiation control signal, for providing control signals to said communication circuit, and said first and second coefficient signals to said rotator.

Claim 3

The processor of claim 1 wherein said means for providing control signals is also responsive to an "inverse" control signal for effecting in said processor a prechosen orthogonal transform processor when said "inverse" control signal is at a first logic level, and for effecting in said processor the inverse transform of said prechosen orthogonal transform when said "inverse" control signal is at a second logic level.

Claim 4

The transform processor of claim 1 wherein said first and second rotator input signals belong to a set of signals that includes said processor input signals and said first and second rotator output signals.

Claim 5

The transform processor of claim 1 wherein said rotator comprises four multipliers, each of which including a plurality of modules, with corresponding modules of said four multipliers being in close physical proximity to each other.

Claim 6

The transform processor of claim 1 wherein said rotator performs four multiplications and comprises an array of interconnected modules, with each module comprising four segments and each segment in a module performing a like portion of the multiplications performed in said rotator.

Claim 7

The transform processor of claim 1 wherein said rotator performs four multiplictions and comprises a matrix of spatially adjacent and interconnected multiplier-adder modules, with each module comprising four segments and each segment in a module performing a like portion of the multiplications performed in said rotator.

Claim 8

The transform processor of claim 1 wherein said rotator performs four multiplications and comprises an matrix of spatially adjacent and interconnected multiplier and adder modules, with each module comprising: a first multiplication logic element responsive to x₀ and c₀; a first adder responsive to applied sum and carry signals and to said first multiplication logic element, for developing an output sum signal and an output carry signal; a second multiplication logic element responsive to x₀ and c₁; a second adder responsive to applied sum and carry signals and to said second multiplication logic element, for developing an output sum signal and an output carry signal; a third multiplication logic element responsive to x₁ and c₀; a third adder responsive to applied sum and carry signals and to said third multiplication logic element, for developing an output sum signal and an output carry signal; a fourth multiplication logic element responsive to x₁ and c₁; and a fourth adder responsive to applied sum and carry signals and to said fourth multiplication logic element, for developing an output sum signal and an output carry signal.

Claim 9

The module of claim 7 further comprising reigster means responsive to said output sum and output carry signals of said first, second, third, and fourth adders and to an applied clock signal, for developing clocked sum and carry output signals of said module.

Claim 10

The module of claim 7 wherein said multiplication logic elements are AND gates.

Claim 11

The transform processor of claim 1 wherein said means for providing control signals comprises; a shift register responsive to said initiation control signal for developing delayed replicas of said initiation control signal; and a plurality of connection point groups, with each group being controlled by a different one of said delayed replicas of said initiation control signal.

Claim 12

The processor of claim 1 wherein said communications circuit comprises: first and second memory segments wherein said first memory segment stores said applied processor input signals and provides said stored processor input signals to said second memory segment under control of said initiation control signal; and said second memory segment, responsive to control signals from said means for developing control signals, stores signals provided by said first memory segment, applies signals to said rotator, stores said output signals of said rotator and, under control of said initiation control signal, applies said transformed output signals to said first memory segment.

Claim 13

The transform processor of claim 1 wherein said rotator comprises four multipliers, each of which including a plurality of modules, with corresponding modules of said four multipliers being in close physical proximity to each other; and adder/subtractor network responsive to some of said modules.