High speed transform circuit

Claim 2

A transform circuit for developing a set of transform signals from a sequence of applied input signals CHARACTERIZED BY A plurality of multipliers (201-215) responsive to said input signals, each multiplying said input signals by a different preselected constant and developing thereby a plurality of product signals; and cyclical pipeline accumulator means (301 etc.) responsive to said plurality of product signals, for adding to or subtracting from a developing set of transform signals said product signals, with said adding to or subtracting from said developing set of transform signals being controlled in accordance with a preselected sequence, and said developing set of transform signals becoming said set of transform signals upon completion of said adding or subtracting.

Claim 3

A transform circuit in accordance with claim 1, wherein said cyclical pipeline accumulator means is CHARACTERIZED BY means for reversing the sign (301-315) of said product signals in accordance with a predetermined sequence for each of said multipliers; and a plurality of pipeline accumulator means (401-415, 501-513) responsive to said means for reversing, for developing said transform signals (c8....c3).

Claim 4

The circuit of claim 2, further CHARACTERIZED BY input signal reordering means interposed between said sequences of said applied input signals and said plurality of constant multipliers.

Claim 5

The circuit of claim 2 further CHARACTERIZED BY output signal reordering means responsive to said transform signals.

Claim 6

The circuit of claim 2, further CHARACTERIZED BY means responsive to said transform signals for receiving said transform in parallel and providing said transform signals serially at an output port of said transform circuit.

Claim 7

The circuit of claim 5 further CHARACTERIZED BY output signal reordering means responsive to said transform signals serially appearing at said output port of said transform circuit.

Claim 8

The circuit of claim 6, further CHARACTERIZED BY input signal reordering means interposed between said sequences of said applied input signals and said plurality of constant multipliers.

Claim 9

The transform circuit of claim 2 wherein each of said pipeline accumulators is CHARACTERIZED BY a plurality of combine-and-store networks (401, 501), each having two inputs and one input, for arithmetically combining signals at said two inputs, storing the combined signals and making the stored signals available at said one output, with said combine-and-store networks connected in a ring, where one of said inputs of each of said combine-and-store networks is connected to said output of another one of said combine-and-store networks, and said second input of each of said combine-and-store networks is responsive to said product signals.

Claim 10

The transform circuit of claim 1 wherein said cyclical pipeline accumulator means is CHARACTERIZED BY a plurality of combine-and-store networks, each having two inputs and one input, for arithmetically combining signals at said two inputs, storing the combined signals and making the stored signals available at said one output, with said combine-and-store networks connected in a ring, where one of said inputs of each of said combine-and-store networks is connected to said output of another one of said combine-and-store networks, and said second input of each of said combine-and-store networks is responsive to said product signals.

Claim 11

A two dimensional transform generator CHARACTERIZED BY a first one-dimensional transform generator responsive to input signals including a first plurality of constant multipliers, for developing sequences of first product signals; first means for reversing the sign of said product signals in accordance with a predetermined sequence for each of said multipliers in said first plurality of multipliers; and a first plurality of cyclical pipeline accumulator means responsive to said first means for reversing, for developing intermediate coefficient signals. an intermediate reordering memory responsive to said intermediate coefficient signals: and a second one-dimensional transform generator including a second plurality of constant multipliers, connected to said intermediate reordering memory, for developing sequences of second product signals; second means for reversing the sign of said second product signals in accordance with a predetermined sequence for each of said multipliers in said second plurality of multipliers; and a second plurality of cyclical pipeline accumulator means responsive to said second means for reversing, for developing final coefficient signals.

Claim 12

A two dimensional transform generator CHARACTERIZED BY a first one-dimensional transform generator responsive to input signals including a first plurality of constant multipliers, for developing sequences of first product signals; first means for reversing the sign of said product signals in accordance with a predetermined sequence for each of said multipliers in said first plurality of multipliers; and a first plurality of cyclical pipeline accumulator means responsive to said first means for reversing, for developing intermediate coefficient signals. an intermediate reordering memory responsive to said intermediate coefficient signals: and a second one-dimensional transform generator including a second plurality of constant multipliers, connected to said intermediate reordering memory, for developing sequences of second product signals; second means for reversing the sign of said second product signals in accordance with a predetermined sequence for each of said multipliers in said second plurality of multipliers; and a second plurality of cyclical pipeline accumulator means responsive to said second means for reversing, for developing final coefficient signals.

Claim 13

The two dimensional transform generator of claim 10 further CHARACTERIZED BY a preprocessing reordering memory interposed between said inputs signals and said first one-dimensional transform generator.

Claim 14

The two dimensional transform generator of claim 10 further CHARACTERIZED BY a postprocessing reordering memory responsive to said final coefficient signals.

Claim 15

The apparatus of claim 11, further CHARACTERIZED BY means for applying image samples to said preprocessing reordering memory to develop discrete cosine transform coefficients at said final set of coefficient signals, and means for compressing said final set of coefficient signals.

Claim 16

The apparatus of claim 12, further CHARACTERIZED BY means for applying discrete cosine transform signals to said first one-dimensional transform generator to develop image samples at said final set of coefficient signals.