US5117385A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Table lookup multiplier with digital filter
Assignee: International Business Machines Corp
•
Filing: 1991-10-08
•
Granted: 1992-05-26
•
Expires: 2011-10-08
Abstract
Abstract In a digital multiplier for multiplying two multi-bit binary operands to produce a binary result by means of a lookup table containing all possible products of said operands, reduction of the total amount of memory required to store the table is obtained by segmenting one operand into a plurality of non-overlapping bit groups and constructing lookup tables for the bit groups, in which each lookup table contains products of its associated bit group and the other, non-partitioned operand. Multiplication is accomplished by generating partial products from the lookup tables, shifting the partial products to account for the relative significance of their associated bit groups, and adding the partial products to provide the resultant product.
Inventors
- 👤 Ralph L. Gee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:45
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5324; G06F1/00; G06F1/02; G06F1/03; G06F1/035; G06F1/0356
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
353 words
A method for look-up multiplication of an m-bit operand X and an 1-bit operand K to reduce an n-bit product Y where n=m+1 and the m bits of X are ordered in significance from bit 1 , the most significant bit (MSB), to bit m , the least significant bit (LSB), the method executable with an addressable storage apparatus and a binary adder, the method including the steps of: partitioning X into consecutive, non-overlapping bit groups, the bit groups forming X when concatenated in a particular magnitude order in which each bit group has a respective magnitude position; the partitioning step including partitioning X into non-overlapping bit groups, such that: ##EQU9## where G is the number of bit groups in X, g i is the number of bits in the ith bit group, and g l is the number of bits in the bit group including the MSB, the maximum size of the bit group being the integer number of bits in the its bit group such that, g.sub.i <(m/G)+1, for all i and, either g 1 alone is the maximum size bit group, g max , if ##EQU10## or, g 1 is the smallest size bit group; generating a set of partial products for each bit group, each partial product representing the multiplication of K by a number which the bit group represents; storing sets of partial products in the addressable storage apparatus such that each partial product of a set is stored at an address location corresponding to the number which is multiplied with K to generate the partial product said partial products including odd multiples of K; presenting X(t) for multiplication by K, X(t) being a particular value of X; obtaining partial products from said storage apparatus in response to X(t), each partial product obtained in response to a respective bit group of X(t) and representing the product of the instantaneous value of that bit group and K; shifting the most significant bit groups in a predetermined magnitude direction with respect to the least significant bit group to form i n-bit partial products; and adding said i n-bit partial products.
Claim 2
Independent Claim
353 words
A method for look-up multiplication of an m-bit operand X and an 1-bit operand K to reduce an n-bit product Y where n=m+1 and the m bits of X are ordered in significance from bit 1 , the most significant bit (MSB), to bit m , the least significant bit (LSB), the method executable with an addressable storage apparatus and a binary adder, the method including the steps of: partitioning X into consecutive, non-overlapping bit groups, the bit groups forming X when concatenated in a particular magnitude order in which each bit group has a respective magnitude position; the partitioning step including partitioning X into non-overlapping bit groups, such that: ##EQU9## where G is the number of bit groups in X, g i is the number of bits in the ith bit group, and g l is the number of bits in the bit group including the MSB, the maximum size of the bit group being the integer number of bits in the its bit group such that, g.sub.i <(m/G)+1, for all i and, either g 1 alone is the maximum size bit group, g max , if ##EQU10## or, g 1 is the smallest size bit group; generating a set of partial products for each bit group, each partial product representing the multiplication of K by a number which the bit group represents; storing sets of partial products in the addressable storage apparatus such that each partial product of a set is stored at an address location corresponding to the number which is multiplied with K to generate the partial product said partial products including odd multiples of K; presenting X(t) for multiplication by K, X(t) being a particular value of X; obtaining partial products from said storage apparatus in response to X(t), each partial product obtained in response to a respective bit group of X(t) and representing the product of the instantaneous value of that bit group and K; shifting the most significant bit groups in a predetermined magnitude direction with respect to the least significant bit group to form i n-bit partial products; and adding said i n-bit partial products.
Claim 3
Dependent Claim
26 words
The method of claim 1, wherein the step of obtaining includes shifting an odd multiple in a predetermined magnitude direction to obtain even multiples of K.
Claim 4
Dependent Claim
249 words
A lookup table multiplier for generating an n-bit number Y representing the product of an m-bit operand X and an 1-bit operand K, where n=m+1 and the m bits of X are ordered in significance from bit 1 , the most significant bit (MSB), to bit m , the least significant bit (LSB), comprising: partial product means for generating a plurality of partial products, each partial product representing the product of K and a number represented by a group of consecutive bits of X, where X is partitioned into G non-overlapping groups of consecutive bits (bit groups) such that ##EQU11## where G is the number o bit groups, g i is the number of bits in he ith bit group, and g l is the number of bits in the bit group including the MSB, the maximum size of a bit group being the largest integer which is less than (m/G) +1 and either g l alone is the maximum size bit group, g max , if ##EQU12## otherwise, g l is the smallest size bit group; addressable storage means connected to the partial product means for storing partial products at address locations corresponding to the numbers by which K is multiplied to generate the partial products said partial products including only odd multiples of K; a converter, connected to the addressable storage means of converting the partial products to partial products; and an adder circuit connected to the converter for adding said n-bit partial products to produce Y.
Claim 5
Dependent Claim
249 words
A lookup table multiplier for generating an n-bit number Y representing the product of an m-bit operand X and an 1-bit operand K, where n=m+1 and the m bits of X are ordered in significance from bit 1 , the most significant bit (MSB), to bit m , the least significant bit (LSB), comprising: partial product means for generating a plurality of partial products, each partial product representing the product of K and a number represented by a group of consecutive bits of X, where X is partitioned into G non-overlapping groups of consecutive bits (bit groups) such that ##EQU11## where G is the number o bit groups, g i is the number of bits in he ith bit group, and g l is the number of bits in the bit group including the MSB, the maximum size of a bit group being the largest integer which is less than (m/G) +1 and either g l alone is the maximum size bit group, g max , if ##EQU12## otherwise, g l is the smallest size bit group; addressable storage means connected to the partial product means for storing partial products at address locations corresponding to the numbers by which K is multiplied to generate the partial products said partial products including only odd multiples of K; a converter, connected to the addressable storage means of converting the partial products to partial products; and an adder circuit connected to the converter for adding said n-bit partial products to produce Y.
Claim 6
Dependent Claim
30 words
The lookup table multiplier of claim 3 further including means connected to the addressable storage means for generating even multiples of K in response to an odd multiple of K.
Claim 7
Dependent Claim
339 words
In a discrete multi-stage filter in which a stage result is produced at the jth stage by combining a prior stage result produced at a stage preceding the jth stage with a stage product, an improved stage architecture for the jth filter stage, the stage architecture comprising; an adder for adding the prior stage result with a stage product to produce a jth stage result; storage connected to he adder for providing the jth stage result to a stage succeeding the jth filter stage; and a stage multiplier connected to the adder for generating an n-bit stage product by multiplying an m-bit operand X and an 1-bit stage co-efficient K, where n=m+1 and the m bits of X are ordered in significance from bit 1 , the most significant bit (MSB), to bit m , the least significant bit (LSB), including: partial product means for generating a plurality of partial products, each partial product representing the product of K and a number represented by a group of consecutive bits of X, where X is partitioned into G non-overlapping groups of consecutive bits (bit groups) such that ##EQU13## where G is the number of bit groups, g i is the number of bits in the ith bit group, and g l is the number of bits in the bit group including the MSB, the maximum size of a bit group being the largest integer which is less than (m/G) +1 and either g l alone is the maximum size bit group, g max , if ##EQU14## otherwise, g l is the smallest size bit group; addressable storage means connected to the partial product means for storing partial products at address locations corresponding to the numbers by which K is multiplied to generate the partial products, said partial products including only odd multiples of K; converter means, connected to the addressable storage means for converting the partial products to n-bit partial products; and an adder circuit connected to the converter for adding said n-bit partial products to produce said stage result.
Claim 8
Dependent Claim
339 words
In a discrete multi-stage filter in which a stage result is produced at the jth stage by combining a prior stage result produced at a stage preceding the jth stage with a stage product, an improved stage architecture for the jth filter stage, the stage architecture comprising; an adder for adding the prior stage result with a stage product to produce a jth stage result; storage connected to he adder for providing the jth stage result to a stage succeeding the jth filter stage; and a stage multiplier connected to the adder for generating an n-bit stage product by multiplying an m-bit operand X and an 1-bit stage co-efficient K, where n=m+1 and the m bits of X are ordered in significance from bit 1 , the most significant bit (MSB), to bit m , the least significant bit (LSB), including: partial product means for generating a plurality of partial products, each partial product representing the product of K and a number represented by a group of consecutive bits of X, where X is partitioned into G non-overlapping groups of consecutive bits (bit groups) such that ##EQU13## where G is the number of bit groups, g i is the number of bits in the ith bit group, and g l is the number of bits in the bit group including the MSB, the maximum size of a bit group being the largest integer which is less than (m/G) +1 and either g l alone is the maximum size bit group, g max , if ##EQU14## otherwise, g l is the smallest size bit group; addressable storage means connected to the partial product means for storing partial products at address locations corresponding to the numbers by which K is multiplied to generate the partial products, said partial products including only odd multiples of K; converter means, connected to the addressable storage means for converting the partial products to n-bit partial products; and an adder circuit connected to the converter for adding said n-bit partial products to produce said stage result.
References Cited (Backward Citations)
US4484299A
Cited
US4573136A
Cited
US4566075A
Cited
US4709343A
Cited
US4679164A
Cited
US4794555A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-26 | 1995-11-25 | 1996-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-26 | 1999-11-25 | 2000-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-26 | 2003-11-25 | 2004-05-26 | $7700.00 | Window Closed / Lapsed |