Patent US5358904A successfully refreshed from Google Patents.
US5358904A
Expired / Lapsed
US
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Semiconductor device
Assignee: Hitachi Ltd
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Filing: 1992-12-14
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Granted: 1994-10-25
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Expires: 2012-12-14
Abstract
Abstract As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
Inventors
- 👤 Gen Murakami
- 👤 Kunihiro Tsubosaki
- 👤 Masahiro Ichitani
- 👤 Kunihiko Nishi
- 👤 Ichiro Anjoh
- 👤 Asao Nishimura
- 👤 Makoto Kitano
- 👤 Akihiro Yaguchi
- 👤 Sueo Kawai
- 👤 Masatsugu Ogata
- 👤 Syuuji Eguchi
- 👤 Hiroyoshi Kokaku
- 👤 Masanori Segawa
- 👤 Hiroshi Hozoji
- 👤 Takashi Yokoyama
- 👤 Noriyuki Kinjo
- 👤 Aizo Kaneda
- 👤 Junichi Saeki
- 👤 Shozo Nakamura
- 👤 Akio Hasebe
- 👤 Hiroshi Kikuchi
- 👤 Isamu Yoshida
- 👤 Takashi Yamazaki
- 👤 Kazuyoshi Oshima
- 👤 Tetsurou Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:21
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/117; H10W; H10W74/00; H10W74/10; H10W74/111; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W70/421; H10W70/424; H10W70/427; H10W70/429; H10W70/435; H10W70/456; H10W70/458; H10W70/461; H10W72/00; H10W72/30; H10W72/90; H10W90/00; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/144; H05K1/18; H05K1/181; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3421; H10W70/60; H10W72/01; H10W72/015; H10W72/01515; H10W72/071; H10W72/072; H10W72/07251; H10W72/075; H10W72/07531; H10W72/07532; H10W72/07533; H10W72/20; H10W72/29; H10W72/321; H10W72/325; H10W72/351; H10W72/352; H10W72/353; H10W72/354; H10W72/381; H10W72/50; H10W72/521; H10W72/522; H10W72/531; H10W72/536; H10W72/5363; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/5525; H10W72/553; H10W72/555; H10W72/59; H10W72/851; H10W72/853; H10W72/865; H10W72/931; H10W72/932; H10W72/934; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952; H10W72/981; H10W72/983; H10W90/20; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
187 words
A method of fabricating a semiconductor device, comprising the steps of: preparing a semiconductor chip having a principle surface with circuit elements and a plurality of external terminals thereon, and only one piece of lead frame having a plurality of leads each comprising an inner lead portion and an outer lead portion, said inner lead portion includes a first region, a second region and a stepped portion between said first region and said second region; bonding said first region of said inner lead portion to said principle surface of said semiconductor chip through an insulating film; electrically connecting each of said leads at said first region of said inner leads to each of said external terminals by wire and molding said chip and said inner lead portions of said plurality of leads by a molding resin in such an arrangement that the chip is supported by said lead frame, wherein a part of said inner lead portion extends to overlap with said semiconductor chip, and distance between said second region and said principle surface being larger than that of between said first region and said principle surface.
Claim 2
Independent Claim
187 words
A method of fabricating a semiconductor device, comprising the steps of: preparing a semiconductor chip having a principle surface with circuit elements and a plurality of external terminals thereon, and only one piece of lead frame having a plurality of leads each comprising an inner lead portion and an outer lead portion, said inner lead portion includes a first region, a second region and a stepped portion between said first region and said second region; bonding said first region of said inner lead portion to said principle surface of said semiconductor chip through an insulating film; electrically connecting each of said leads at said first region of said inner leads to each of said external terminals by wire and molding said chip and said inner lead portions of said plurality of leads by a molding resin in such an arrangement that the chip is supported by said lead frame, wherein a part of said inner lead portion extends to overlap with said semiconductor chip, and distance between said second region and said principle surface being larger than that of between said first region and said principle surface.
Claim 3
Dependent Claim
79 words
A method of fabricating a semiconductor device according to claim 1, wherein said lead frame has a common lead including an inner portion and an outer portion, said inner portion of said common lead is arranged between said first region of said inner lead portion and said external terminals, and wherein said electrically connecting is performed by wire, one of said wire being bonded said external terminal to said first region so as to cross said common inner lead.
Claim 4
Dependent Claim
40 words
A method of fabricating a semiconductor device according to claim 1, further comprising: molding said plurality of external terminals, said electrically connecting means and a part of said principle surface of said chip by a substance before said molding step.
Claim 5
Dependent Claim
18 words
A method of fabricating a semiconductor device according to claim 3, wherein said substance is a flexible/fluid substance.
Claim 6
Dependent Claim
39 words
A method of fabricating a semiconductor device according to claim 1, wherein said lead frame includes leads for supporting said chip, said method further comprising adhering and fixing the principle surface of the semiconductor chip to said supporting leads.
Claim 7
Independent Claim
194 words
A method of fabricating a semiconductor device, comprising the steps of: preparing a semiconductor chip having a principle surface with circuit elements and a plurality of external terminals thereon, and only one piece of lead frame having a plurality of leads each comprising an inner lead portion and an outer lead portion, said inner lead portion includes a first region, a second region and a stepped portion between said first region and said second region; bonding an insulating film to said plurality of leads at a part of said each first regions; bonding said insulating film to said principle surface through an adhesive; electrically connecting each of said leads at said first region of said inner leads to each of said external terminals by wire and molding said chip and said inner lead portions of said plurality of leads by a molding resin in such an arrangement that the chip is supported by said lead frame; wherein a part of said inner lead portion extends to overlap with said semiconductor chip, and distance between said second region and said principle surface being larger than that of between said first region and said principle surface.
Claim 8
Independent Claim
194 words
A method of fabricating a semiconductor device, comprising the steps of: preparing a semiconductor chip having a principle surface with circuit elements and a plurality of external terminals thereon, and only one piece of lead frame having a plurality of leads each comprising an inner lead portion and an outer lead portion, said inner lead portion includes a first region, a second region and a stepped portion between said first region and said second region; bonding an insulating film to said plurality of leads at a part of said each first regions; bonding said insulating film to said principle surface through an adhesive; electrically connecting each of said leads at said first region of said inner leads to each of said external terminals by wire and molding said chip and said inner lead portions of said plurality of leads by a molding resin in such an arrangement that the chip is supported by said lead frame; wherein a part of said inner lead portion extends to overlap with said semiconductor chip, and distance between said second region and said principle surface being larger than that of between said first region and said principle surface.
Claim 9
Dependent Claim
79 words
A method of fabricating a semiconductor device according to claim 6, wherein said lead frame has a common lead including an inner portion and an outer portion, said inner portion of said common lead is arranged between said first region of said inner lead portion and said external terminals, and wherein said electrically connecting is performed by wire, one of said wire being bonded said external terminal to said first region so as to cross said common inner lead.
Claim 10
Dependent Claim
40 words
A method of fabricating a semiconductor device according to claim 6, further comprising: molding said plurality of external terminals, said electrically connecting means and a part of said principle surface of said chip by a substance before said molding step.
Claim 11
Dependent Claim
18 words
A method of fabricating a semiconductor device according to claim 8, wherein said substance is a flexible/fluid substance.
Claim 12
Dependent Claim
39 words
A method of fabricating a semiconductor device according to claim 6, wherein said lead frame includes leads for supporting said chip, said method further comprising adhering and fixing the principle surface of the semiconductor chip to said supporting leads.
Claim 13
Independent Claim
182 words
A method of fabricating a semiconductor device, comprising the steps of: preparing a semiconductor chip having a principle surface with circuit elements and a plurality of external terminals thereon, and only one piece of lead frame having a plurality of leads each comprising an inner lead portion and an outer lead portion, said inner lead portion includes a first region with an insulating film, a second region and a stepped portion between said first region and said second region; bonding said insulating film to said principle surface of said semiconductor chip; electrically connecting each of said leads at said first region of said inner leads to each of said external terminals by wire and molding said chip and said inner lead portions of said plurality of leads by a molding resin in such an arrangement that the chip is supported by said lead frame; wherein a part of said inner lead portion extends to overlap with said semiconductor chip, and distance between said second region and said principle surface being larger than that of between said first region and said principle surface.
Claim 14
Independent Claim
182 words
A method of fabricating a semiconductor device, comprising the steps of: preparing a semiconductor chip having a principle surface with circuit elements and a plurality of external terminals thereon, and only one piece of lead frame having a plurality of leads each comprising an inner lead portion and an outer lead portion, said inner lead portion includes a first region with an insulating film, a second region and a stepped portion between said first region and said second region; bonding said insulating film to said principle surface of said semiconductor chip; electrically connecting each of said leads at said first region of said inner leads to each of said external terminals by wire and molding said chip and said inner lead portions of said plurality of leads by a molding resin in such an arrangement that the chip is supported by said lead frame; wherein a part of said inner lead portion extends to overlap with said semiconductor chip, and distance between said second region and said principle surface being larger than that of between said first region and said principle surface.
Claim 15
Dependent Claim
78 words
A method of fabricating a semiconductor device according to claim 11, wherein said lead frame has a common lead including an inner portion and an outer portion, said inner portion of said common lead is arranged between said first region of said inner lead portion and said external terminals, and wherein said electrically connecting is performed by wire, one of said wire bonding said external terminal to said first region so as to cross said common inner lead.
Claim 16
Dependent Claim
40 words
A method of fabricating a semiconductor device according to claim 11, further comprising: molding said plurality of external terminals, said electrically connecting means and a part of said principle surface of said chip by a substance before said molding step.
Claim 17
Dependent Claim
18 words
A method of fabricating a semiconductor device according to claim 13, wherein said substance is a flexible/fluid substance.
Claim 18
Dependent Claim
39 words
A method of fabricating a semiconductor device according to claim 11, wherein said lead frame includes leads for supporting said chip, said method further comprising adhering and fixing the principle surface of the semiconductor chip to said supporting leads.
References Cited (Backward Citations)
US3783348A
Cited
US4203792A
Cited
US4209355A
Cited
US4355463A
Cited
JPS5745961A
Cited
US4637130A
Cited
US4661837A
Cited
JPS5943534A
Cited
JPS5992556A
Cited
JPS60167454A
Cited
JPS60208847A
Cited
JPS61236130A
Cited
JPS61241959A
Cited
US4862245A
Cited
US4807018A
Cited
US4684975A
Cited
JPS6344749A
Cited
US4809053A
Cited
JPS63211744A
Cited
US4796078A
Cited
US5068712A
Cited
US4996587A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-24 | 1998-04-25 | 1998-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-24 | 2002-04-25 | 2002-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-24 | 2006-04-25 | 2006-10-25 | $7700.00 | Window Closed / Lapsed |