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US5357472A
Expired / Lapsed
US
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Non-volatile semiconductor memory device
Assignee: Renesas Electronics Corp
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Filing: 1993-03-15
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Granted: 1994-10-18
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Expires: 2013-03-15
Abstract
Abstract For directly observing from the outside the electrical characteristics of a memory cell, i.e., a voltage-current characteristic and threshold voltage in a non-volatile semiconductor memory device, there are provided same bit train selector means 5 for selecting and switching on a plurality of bit train selecting FETs(QB o , QB 1 . . . , QB n ) each for interconnecting an external terminal 4 to which arbitrary voltage is applied and respective memory cell arrays 1a, 1b, . . . , 1n with each other and forming a current path extending from a specific memory cell FET (Q 1 ) on the same bit train memory cell array to the external terminal, and a power supply circuit for supplying variable voltage to a gate of the specific memory cell FET (Q i ). Hereby, there are improved the yield of articles and the accuracy of failure article analyses.
Inventors
- 👤 Shozo Shirota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 06:00
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C29/50004; G06; G06F; G06F2201/00; G06F2201/81; G11C16/00; G11C16/02; G11C16/04; G11C2029/5006
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
323 words
A non-volatile semiconductor memory device comprising: a plurality of memory cell arrays coupled to a data bus, each said memory cell array comprising a plurality of memory cells, said plurality of memory cells comprising field effect transistors having a gate width; a word line selector circuit for designating a word line of each said memory cell array and activating a gate electrode of said memory cell connected to a designated word line; a plurality of bit line switching elements for interconnecting said data bus and said memory cell arrays, said plurality of bit line switching elements comprising field effect transistors, wherein a gate width of said plurality of bit line switching elements is much greater than said gate width of said plurality of memory cells; a bit line selector circuit for designating a bit line of each said memory cell array and activating a gate electrode of one of said plurality of bit line switching elements, whereby data in any memory cell in each said memory cell array selected by each said selector circuit is read out or written in through said data bus; an external terminal for receiving an arbitrary input voltage; a plurality of same bit train switching elements for interconnecting said external terminal and said data bus, said plurality of same bit train switching elements comprising field effect transistors, wherein a gate width of said plurality of same bit train switching elements is greater than said gate width of said plurality of memory cells; and same bit train selector means for selecting and activating a gate electrode of one of said plurality of same bit train switching elements and forming a current path extending from a specific memory cell in said memory cell arrays of a selected same bit train to said external terminal, whereby a current is driven to flow through said specific memory cell via said current path by applying said arbitrary input voltage to said external terminal.
Claim 2
Dependent Claim
323 words
A non-volatile semiconductor memory device comprising: a plurality of memory cell arrays coupled to a data bus, each said memory cell array comprising a plurality of memory cells, said plurality of memory cells comprising field effect transistors having a gate width; a word line selector circuit for designating a word line of each said memory cell array and activating a gate electrode of said memory cell connected to a designated word line; a plurality of bit line switching elements for interconnecting said data bus and said memory cell arrays, said plurality of bit line switching elements comprising field effect transistors, wherein a gate width of said plurality of bit line switching elements is much greater than said gate width of said plurality of memory cells; a bit line selector circuit for designating a bit line of each said memory cell array and activating a gate electrode of one of said plurality of bit line switching elements, whereby data in any memory cell in each said memory cell array selected by each said selector circuit is read out or written in through said data bus; an external terminal for receiving an arbitrary input voltage; a plurality of same bit train switching elements for interconnecting said external terminal and said data bus, said plurality of same bit train switching elements comprising field effect transistors, wherein a gate width of said plurality of same bit train switching elements is greater than said gate width of said plurality of memory cells; and same bit train selector means for selecting and activating a gate electrode of one of said plurality of same bit train switching elements and forming a current path extending from a specific memory cell in said memory cell arrays of a selected same bit train to said external terminal, whereby a current is driven to flow through said specific memory cell via said current path by applying said arbitrary input voltage to said external terminal.
Claim 3
Dependent Claim
49 words
The non-volatile semiconductor memory device of claim 1, wherein said bit line selector circuit applies to said gate electrode of one of said plurality of bit line switching elements a voltage greater than a voltage applied to said gate electrode of said memory cell via said designated word line.
Claim 4
Dependent Claim
51 words
The non-volatile semiconductor memory device of claim 1, wherein said same bit train selector means applies to said gate electrode of one of said plurality of same bit train switching elements a voltage greater than a voltage applied to said gate electrode of said memory cell via said designated word line.
Claim 5
Dependent Claim
362 words
A non-volatile semiconductor memory device comprising: a plurality of memory cell arrays coupled to a data bus, each said memory cell array comprising a plurality of memory cells, said plurality of memory cells comprising field effect transistors having a gate width; a word line selector circuit for designating a word line of each said memory cell array and activating a gate electrode of said memory cell connected to a designated word line; a plurality of bit line switching elements for interconnecting said data bus and said memory cell arrays, said plurality of bit line switching elements comprising field effect transistors, wherein a gate width of said plurality of bit line switching elements is greater than said gate width of said plurality of memory cells; a bit line selector circuit for designating a bit line of each said memory cell array and activating a gate electrode of one of said plurality of bit line switching elements, whereby data in any memory cell in each said memory cell array selected by each said selector circuit is read out or written in through said data bus; an external terminal for receiving an arbitrary input voltage; a plurality of same bit train switching elements for interconnecting said external terminal and said data bus, said plurality of same bit train switching elements comprising field effect transistors, wherein a gate width of said plurality of same bit train switching elements is greater than said gate width of said plurality of memory cells; same bit train selector means for selecting and activating a gate electrode of one of said plurality of same bit train switching elements and forming a current path extending from a specific memory cell in said memory cell arrays of a selected same bit train to said external terminal, whereby a current is driven to flow through said specific memory cell via said current path by applying said arbitrary input voltage to said external terminal; and a power supply circuit for supplying to said gate electrode of said specific memory cell a variable voltage via said word line designated by said word line selector circuit, whereby a threshold voltage of said specific memory cell is measured.
Claim 6
Dependent Claim
362 words
A non-volatile semiconductor memory device comprising: a plurality of memory cell arrays coupled to a data bus, each said memory cell array comprising a plurality of memory cells, said plurality of memory cells comprising field effect transistors having a gate width; a word line selector circuit for designating a word line of each said memory cell array and activating a gate electrode of said memory cell connected to a designated word line; a plurality of bit line switching elements for interconnecting said data bus and said memory cell arrays, said plurality of bit line switching elements comprising field effect transistors, wherein a gate width of said plurality of bit line switching elements is greater than said gate width of said plurality of memory cells; a bit line selector circuit for designating a bit line of each said memory cell array and activating a gate electrode of one of said plurality of bit line switching elements, whereby data in any memory cell in each said memory cell array selected by each said selector circuit is read out or written in through said data bus; an external terminal for receiving an arbitrary input voltage; a plurality of same bit train switching elements for interconnecting said external terminal and said data bus, said plurality of same bit train switching elements comprising field effect transistors, wherein a gate width of said plurality of same bit train switching elements is greater than said gate width of said plurality of memory cells; same bit train selector means for selecting and activating a gate electrode of one of said plurality of same bit train switching elements and forming a current path extending from a specific memory cell in said memory cell arrays of a selected same bit train to said external terminal, whereby a current is driven to flow through said specific memory cell via said current path by applying said arbitrary input voltage to said external terminal; and a power supply circuit for supplying to said gate electrode of said specific memory cell a variable voltage via said word line designated by said word line selector circuit, whereby a threshold voltage of said specific memory cell is measured.
Claim 7
Dependent Claim
59 words
The non-volatile semiconductor memory device of claim 4, wherein said power supply circuit comprises: an external terminal for receiving said variable voltage; a power supply voltage; a power supply switching circuit for supplying a selected voltage to said word line selector circuit; and a switching signal line for selecting one of said variable voltage and said power supply voltage.
Claim 8
Dependent Claim
49 words
The non-volatile semiconductor memory device of claim 4, wherein said bit line selector circuit applies to said gate electrode of one of said plurality of bit line switching elements a voltage greater than a voltage applied to said gate electrode of said memory cell via said designated word line.
Claim 9
Dependent Claim
51 words
The non-volatile semiconductor memory device of claim 4, wherein said same bit train selector means applies to said gate electrode of one of said plurality of same bit train switching elements a voltage greater than a voltage applied to said gate electrode of said memory cell via said designated word line.
Claim 10
Independent Claim
180 words
A method of measuring electrical characteristics of a specific memory cell in a non-volatile semiconductor memory device directly, comprising the steps of: designating a word line in the non-volatile semiconductor memory device using a word line selector circuit; designating a bit line in the non-volatile semiconductor memory device using a bit line selector circuit; selecting the specific memory cell by designating said word line and said bit line; designating a same bit train and activating a same bit train switching element using a same bit train selector circuit, forming a current path extending from the specific memory cell of said designated same bit train to an external terminal, bypassing a write amplifier in said semiconductor memory device; applying an arbitrary input voltage to said external terminal, whereby a current is driven to flow through said specific memory cell via said current path by applying said arbitrary input voltage to said external terminal; and observing the current response of said specific memory cell to said arbitrary input voltage at said external terminal, bypassing a sense amplifier in said semiconductor memory device.
Claim 11
Independent Claim
180 words
A method of measuring electrical characteristics of a specific memory cell in a non-volatile semiconductor memory device directly, comprising the steps of: designating a word line in the non-volatile semiconductor memory device using a word line selector circuit; designating a bit line in the non-volatile semiconductor memory device using a bit line selector circuit; selecting the specific memory cell by designating said word line and said bit line; designating a same bit train and activating a same bit train switching element using a same bit train selector circuit, forming a current path extending from the specific memory cell of said designated same bit train to an external terminal, bypassing a write amplifier in said semiconductor memory device; applying an arbitrary input voltage to said external terminal, whereby a current is driven to flow through said specific memory cell via said current path by applying said arbitrary input voltage to said external terminal; and observing the current response of said specific memory cell to said arbitrary input voltage at said external terminal, bypassing a sense amplifier in said semiconductor memory device.
Claim 12
Independent Claim
127 words
A method of measuring a threshold voltage of a specific memory cell in a non-volatile semiconductor memory device, comprising the steps of: designating a word line in the non-volatile semiconductor memory device using a word line selector circuit; designating a bit line in the non-volatile semiconductor memory device using a bit line selector circuit; selecting the specific memory cell by designating said word line and said bit line; supplying a variable voltage to the non-volatile semiconductor memory device on an external terminal; selecting one of a power supply voltage and said variable voltage as a selected voltage to be applied to the specific memory cell; applying said selected voltage on said word line to the specific memory cell; measuring the threshold voltage of the specific memory cell.
Claim 13
Independent Claim
127 words
A method of measuring a threshold voltage of a specific memory cell in a non-volatile semiconductor memory device, comprising the steps of: designating a word line in the non-volatile semiconductor memory device using a word line selector circuit; designating a bit line in the non-volatile semiconductor memory device using a bit line selector circuit; selecting the specific memory cell by designating said word line and said bit line; supplying a variable voltage to the non-volatile semiconductor memory device on an external terminal; selecting one of a power supply voltage and said variable voltage as a selected voltage to be applied to the specific memory cell; applying said selected voltage on said word line to the specific memory cell; measuring the threshold voltage of the specific memory cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-17 | 1998-04-18 | 1998-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-17 | 2002-04-18 | 2002-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-17 | 2006-04-18 | 2006-10-18 | $7700.00 | Window Closed / Lapsed |