Patent US5717253A successfully refreshed from Google Patents.
Patent US5355020A successfully refreshed from Google Patents.
US5355020A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having a multi-layer metal contact
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-07-08
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Granted: 1994-10-11
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Expires: 2012-07-08
Abstract
Abstract A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via) and a first conductive layer formed on the insulating layer which completely fills the opening. The first conductive layer does not produce any Si precipitates in a subsequent heat-treating step for filling the opening with the first conductive layer material. The semiconductor device may further include a second conductive layer having a planarized surface on the first conductive layer. This improves subsequent photolithography. An anti-reflective layer may be formed on the second conductive layer for preventing an unwanted reflection during a photo lithography process. The semiconductor device preferably includes a diffusion barrier layer under the first conductive layer and on the semiconductor substrate, on the insulating layer, and on the inner surface of the opening which prevents a reaction between the first conductive layer and the semiconductor substrate or the insulating layer. A method for forming the wiring layer is also disclosed. Providing a semiconductor device with the wiring layer reduces the leakage current by preventing an Al spiking. Since the first conductive layer undergoes a heat-treatment step at a temperature below the melting point, while flowing into the opening and completely filling it with the first conductive layer material, no void is formed in the opening. Good semiconductor device reliability is ensured in spite of the contact hole being less than 1 mu m in size and having an aspect ratio greater than 1.0.
Inventors
- 👤 Sang-in Lee
- 👤 Jeong-in Hong
- 👤 Jong-Ho Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:57
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/033; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10P; H10P76/00; H10P76/20; H10P76/204; H10P76/2041; H10P76/2043; H10W20/047; H10W20/049; H10W20/052; H10W20/0526; H10W20/056; H10W20/057; H10W20/059; H10W20/063; H10W20/0633; H10W20/064; H10W20/066; H10W20/40; H10W20/41; H10W20/425; H10W20/44; H10W20/4403; H10W20/4405; H10W20/4451
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
200 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface and a second metal layer formed on said first metal layer, said first metal layer being comprised of a material having a Si component and selected from a group consisting of an Al--Si alloy and an Al--Cu--Si alloy and said second metal layer being comprised of a material having no Si component and selected from a group consisting of pure aluminum, an Al--Cu alloy and an Al--Ti alloy, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer.
Claim 2
Dependent Claim
200 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface and a second metal layer formed on said first metal layer, said first metal layer being comprised of a material having a Si component and selected from a group consisting of an Al--Si alloy and an Al--Cu--Si alloy and said second metal layer being comprised of a material having no Si component and selected from a group consisting of pure aluminum, an Al--Cu alloy and an Al--Ti alloy, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer.
Claim 3
Dependent Claim
30 words
The semiconductor device as set forth in claim 1, further comprising a diffusion barrier layer formed on said insulating layer, said inner surface of said hole and said underlying surface.
Claim 4
Dependent Claim
31 words
The semiconductor device as set forth in claim 2, wherein said diffusion barrier layer is comprised of a material selected from a group consisting of transition metals and transition metal compounds.
Claim 5
Dependent Claim
30 words
The semiconductor device as set forth in claim 1, further comprising a diffusion barrier layer formed on said insulating layer, said inner surface of said hole and said underlying surface.
Claim 6
Dependent Claim
202 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, said first metal layer being comprised of a material having a Si component and a second metal layer formed on said first metal layer, and said second metal layer being comprised of a material having no Si component, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer, and said first conductive layer has a thickness of about one-third to two-thirds of a predetermined thickness of said wiring layer.
Claim 7
Dependent Claim
202 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, said first metal layer being comprised of a material having a Si component and a second metal layer formed on said first metal layer, and said second metal layer being comprised of a material having no Si component, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer, and said first conductive layer has a thickness of about one-third to two-thirds of a predetermined thickness of said wiring layer.
Claim 8
Dependent Claim
30 words
The semiconductor device as set forth in claim 5, further comprising a diffusion barrier layer formed on said insulating layer, said inner surface of said hole and said underlying surface.
Claim 9
Dependent Claim
211 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, said first metal layer being comprised of a material having a Si component and said second metal layer being comprised of a material having no Si component, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer; and, wherein said first metal layer has a thickness not more than one-quarter of a predetermined thickness of said wiring layer, and said second metal layer has a thickness not less than five-twelfths of said predetermined thickness of said wiring layer.
Claim 10
Dependent Claim
211 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, said first metal layer being comprised of a material having a Si component and said second metal layer being comprised of a material having no Si component, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer; and, wherein said first metal layer has a thickness not more than one-quarter of a predetermined thickness of said wiring layer, and said second metal layer has a thickness not less than five-twelfths of said predetermined thickness of said wiring layer.
Claim 11
Dependent Claim
30 words
The semiconductor device as set forth in claim 7, further comprising a diffusion barrier layer formed on said insulating layer, said inner surface of said hole and said underlying surface.
Claim 12
Dependent Claim
190 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, said first metal layer being comprised of a refractory metal silicide material and said second metal layer being comprised of a metal selected from a group consisting of metal having no Si component and a metal having not more than 0.5% by weight of a Si component, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer.
Claim 13
Dependent Claim
190 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, said first metal layer being comprised of a refractory metal silicide material and said second metal layer being comprised of a metal selected from a group consisting of metal having no Si component and a metal having not more than 0.5% by weight of a Si component, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer.
Claim 14
Dependent Claim
21 words
The semiconductor device as set forth in claim 9, wherein said first metal layer has a thickness of about 200-1,000 angstroms.
Claim 15
Dependent Claim
34 words
The semiconductor device as set forth in claim 9, wherein said refractory metal silicide material selected from a group consisting of WSi 2 , MoSi 2 , TiSi 2 , and TaSi 2 .
Claim 16
Dependent Claim
48 words
The semiconductor device as set forth in claim 9, wherein said second metal layer is comprised of a metal selected from a group consisting of pure aluminum, an Al--Cu alloy, an Al--Ti alloy, and an aluminum alloy having not more than 0.5% by weight of a Si component.
Claim 17
Dependent Claim
28 words
The semiconductor device as set forth in claim 9, wherein said second metal layer has a thickness of one-third to two-thirds a predetermined thickness of said wiring layer.
Claim 18
Dependent Claim
30 words
The semiconductor device as set forth in claim 9, further comprising a diffusion barrier layer formed on said insulating layer, said inner surface of said hole and said underlying surface.
Claim 19
Dependent Claim
168 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, said first metal layer being comprised of a refractory metal material and said second metal layer being comprised of a metal having a Si component, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer.
Claim 20
Dependent Claim
168 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, said first metal layer being comprised of a refractory metal material and said second metal layer being comprised of a metal having a Si component, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer.
Claim 21
Dependent Claim
30 words
The semiconductor device as set forth in claim 15, wherein said refractory metal material is comprised of a metal selected from a group consisting of Ti, Mo, W and Ta.
Claim 22
Dependent Claim
21 words
The semiconductor device as set forth in claim 15, wherein said first metal layer has a thickness of below 500 angstroms.
Claim 23
Dependent Claim
21 words
The semiconductor device as set forth in claim 16, wherein said refactory metal material has a thickness of about 100-300 angstroms.
Claim 24
Dependent Claim
28 words
The semiconductor device as set forth in claim 15, wherein said second metal layer has a thickness of about 10-80% of a predetermined thickness of said wiring layer.
Claim 25
Dependent Claim
32 words
The semiconductor device as set forth in claim 15, wherein said second metal layer is comprised of a metal selected from a group consisting of an Al--Si alloy and an Al--Cu--Si alloy.
Claim 26
Dependent Claim
20 words
The semiconductor device as set forth in claim 20, further comprising an anti-reflective layer formed on said second conductive layer.
Claim 27
Dependent Claim
20 words
The semiconductor device as set forth in claim 21, wherein said anti-reflective layer is comprised of a transition metal compound.
Claim 28
Dependent Claim
30 words
The semiconductor device as set forth in claim 15, further comprising a diffusion barrier layer formed on said insulating layer, said inner surface of said hole and said underlying surface.
Claim 29
Dependent Claim
172 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, said second metal layer being comprised of a metal having no Si component and selected from a group consisting of pure aluminum, an Al--Cu alloy and an Al--Ti alloy, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer.
Claim 30
Dependent Claim
172 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, said second metal layer being comprised of a metal having no Si component and selected from a group consisting of pure aluminum, an Al--Cu alloy and an Al--Ti alloy, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer.
Claim 31
Dependent Claim
30 words
The semiconductor device as set forth in claim 24, wherein said second conductive layer has a thickness of about one-third to two-thirds of a predetermined thickness of said wiring layer.
Claim 32
Dependent Claim
30 words
The semiconductor device as set forth in claim 24, further comprising a diffusion barrier layer formed on said insulating layer, said inner surface of said hole and said underlying surface.
Claim 33
Dependent Claim
156 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer; and, wherein said opening comprises a contact hole with a step formed thereon.
Claim 34
Dependent Claim
156 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer; and, wherein said opening comprises a contact hole with a step formed thereon.
Claim 35
Dependent Claim
30 words
The semiconductor device as set forth in claim 27, further comprising a diffusion barrier layer formed on said insulating layer, said inner surface of said hole and said underlying surface.
Claim 36
Dependent Claim
152 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer; and, wherein said opening comprises a tapered contact hole.
Claim 37
Dependent Claim
152 words
A semiconductor device including a wiring layer, comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening exposing a portion of a surface underlying said insulating layer; a first conductive layer formed on said insulating layer and completely filling said opening, said first conductive layer being comprised of a first metal layer formed on an inner surface of said opening, on said insulating layer, and on said exposed portion of said underlying surface, and a second metal layer formed on said first metal layer, wherein said first conductive layer does not produce Si precipitates when subjected to cooling following heat treatment for completely filling said opening with said first conductive layer; a second conductive layer having a planarized surface; and, wherein said first conductive layer and said second conductive layer together comprise said wiring layer; and, wherein said opening comprises a tapered contact hole.
Claim 38
Dependent Claim
30 words
The semiconductor device as set forth in claim 29, further comprising a diffusion barrier layer formed on said insulating layer, said inner surface of said hole and said underlying surface.
Claim 39
Dependent Claim
124 words
A semiconductor device including a wiring layer comprising: a semiconductor substrate having an impurity-doped region; an insulating layer having a contact hole formed on said impurity-doped region of said semiconductor substrate, said contact hole having an aspect ratio grater than 1.0; a first conductive layer comprised of a refractory metal silicide layer formed on an inner surface of said contact hole, on a surface of said insulating layer and on an exposed surface of said semiconductor substrate, a metal layer having no Si component formed on said refractory metal layer, and said metal layer completely filling said contact hole; and a second conductive layer having a planarized surface formed on said first conductive layer and being comprised of a metal having no Si component.
Claim 40
Dependent Claim
124 words
A semiconductor device including a wiring layer comprising: a semiconductor substrate having an impurity-doped region; an insulating layer having a contact hole formed on said impurity-doped region of said semiconductor substrate, said contact hole having an aspect ratio grater than 1.0; a first conductive layer comprised of a refractory metal silicide layer formed on an inner surface of said contact hole, on a surface of said insulating layer and on an exposed surface of said semiconductor substrate, a metal layer having no Si component formed on said refractory metal layer, and said metal layer completely filling said contact hole; and a second conductive layer having a planarized surface formed on said first conductive layer and being comprised of a metal having no Si component.
Claim 41
Dependent Claim
121 words
A semiconductor device including a wiring layer comprising: a semiconductor substrate having an impurity-doped region; an insulating layer having a contact hole formed on said impurity-doped region of said semiconductor substrate, said contact hole having an aspect ratio greater than 1.0; a first conductive layer comprised of a refractory metal layer formed on an inner surface of said contact hole, on a surface of said insulating layer and on an exposed surface of said semiconductor substrate and a metal layer having a Si component, formed on said refractory metal layer and completely filling said contact hole; and a second conductive layer having a planarized surface formed on said first conductive layer and being comprised of a metal having no Si component.
Claim 42
Dependent Claim
121 words
A semiconductor device including a wiring layer comprising: a semiconductor substrate having an impurity-doped region; an insulating layer having a contact hole formed on said impurity-doped region of said semiconductor substrate, said contact hole having an aspect ratio greater than 1.0; a first conductive layer comprised of a refractory metal layer formed on an inner surface of said contact hole, on a surface of said insulating layer and on an exposed surface of said semiconductor substrate and a metal layer having a Si component, formed on said refractory metal layer and completely filling said contact hole; and a second conductive layer having a planarized surface formed on said first conductive layer and being comprised of a metal having no Si component.
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