Multilayer polysilicon gate self-align process for VLSI CMOS device

Claim 1

The method of forming a self-aligned polysilicon gate in an integrated circuit comprising: forming field silicon oxide regions in and on a semiconductor substrate; forming a gate silicon oxide layer overlying said semiconductor substrate between said field silicon oxide regions; depositing a first layer of polysilicon overlying said gate silicon oxide; forming a native silicon oxide layer having a thickness greater than 5 Angstroms over said first polysilicon layer; depositing a second layer of polysilicon over said native silicon oxide layer wherein silicon grain boundaries of said second layer of polysilicon are misaligned with silicon grain boundaries of said first layer of polysilicon; a first annealing of said silicon substrate at a temperature of more than about 800° C. whereby silicon oxide gas from said native silicon oxide layer is exhausted effectively removing said native silicon oxide layer; etching away said polysilicon layers not covered by a mask to form said polysilicon gate; implanting a first set of ions into said semiconductor substrate using said gate as a mask; forming spacers on the vertical sidewalls of said gate; implanting a second set of ions into said substrate using said gate as a mask wherein said mask is effective because said misaligned silicon grain boundaries of said polysilicon layers do not allow said ions to diffuse into said silicon substrate under said mask; implanting a third set of ions into said substrate using said gate as a mask; a second annealing of said semiconductor substrate to simultaneously activate said first, second, and third set of implanted ions; depositing an insulating layer over said gate, gate silicon oxide, and field silicon oxide regions; and providing by metallization techniques electrical connections to complete formation of said integrated circuit.

Claim 2

The method of forming a self-aligned polysilicon gate in an integrated circuit comprising: forming field silicon oxide regions in and on a semiconductor substrate; forming a gate silicon oxide layer overlying said semiconductor substrate between said field silicon oxide regions; depositing a first layer of polysilicon overlying said gate silicon oxide; forming a native silicon oxide layer having a thickness greater than 5 Angstroms over said first polysilicon layer; depositing a second layer of polysilicon over said native silicon oxide layer wherein silicon grain boundaries of said second layer of polysilicon are misaligned with silicon grain boundaries of said first layer of polysilicon; a first annealing of said silicon substrate at a temperature of more than about 800° C. whereby silicon oxide gas from said native silicon oxide layer is exhausted effectively removing said native silicon oxide layer; etching away said polysilicon layers not covered by a mask to form said polysilicon gate; implanting a first set of ions into said semiconductor substrate using said gate as a mask; forming spacers on the vertical sidewalls of said gate; implanting a second set of ions into said substrate using said gate as a mask wherein said mask is effective because said misaligned silicon grain boundaries of said polysilicon layers do not allow said ions to diffuse into said silicon substrate under said mask; implanting a third set of ions into said substrate using said gate as a mask; a second annealing of said semiconductor substrate to simultaneously activate said first, second, and third set of implanted ions; depositing an insulating layer over said gate, gate silicon oxide, and field silicon oxide regions; and providing by metallization techniques electrical connections to complete formation of said integrated circuit.

Claim 17

The method of constructing a multilayer polysilicon gate wherein said gate acts as a mask for ion implantation comprising: providing on a semiconductor substrate a layer of gate silicon oxide; depositing a first layer of polysilicon over said layer of gate silicon oxide; forming at least one layer of native silicon oxide having a thickness of between about 5 to 50 Angstroms on top of said polysilicon layer; and depositing at least one second layer of polysilicon over said native silicon oxide layer whereby silicon grain boundaries of said first and at least one second layer of polysilicon will be misaligned thereby providing an effective mask for high energy ion implantation of between about 60 to 120 KeV, and removing said native silicon oxide by annealing at a temperature of between about 800° to 1000° C. in a vacuum before ion implantation.

Claim 18

The method of constructing a multilayer polysilicon gate wherein said gate acts as a mask for ion implantation comprising: providing on a semiconductor substrate a layer of gate silicon oxide; depositing a first layer of polysilicon over said layer of gate silicon oxide; forming at least one layer of native silicon oxide having a thickness of between about 5 to 50 Angstroms on top of said polysilicon layer; and depositing at least one second layer of polysilicon over said native silicon oxide layer whereby silicon grain boundaries of said first and at least one second layer of polysilicon will be misaligned thereby providing an effective mask for high energy ion implantation of between about 60 to 120 KeV, and removing said native silicon oxide by annealing at a temperature of between about 800° to 1000° C. in a vacuum before ion implantation.