Interrupt control system for microprocessor for handling a plurality of maskable interrupt requests

Claim 1

An interrupt control system for use in a microprocessor configured to sequentially execute an instruction indicated by a program counter and to be able to process a plurality of interrupt requests, the interrupt control system including: first receiving means for receiving an interrupt request signal from an external source, second receiving means for receiving from the external source a plurality of signal lines weighted to indicate a level of said interrupt request signal, status hold means having a group of flags which include a plurality of flags indicative of an interrupt allowing level and one flag indicating a predetermined status of an interrupt request, first save means for temporarily saving a content of said status hold means in its entirety in said microprocessor, second save means for temporarily saving a content of said program counter in said microprocessor, status indicating means for indicating that the interrupt request is acknowledged, comparison means for comparing the interrupt allowing level indicated by said group of flags, with said level received by said second receiving means so as to determine a large-and-small relation therebetween, and control means for controlling said status hold means, said first and second save means and said status indicating means, whereby when an interrupt request is supplied to said first receiving means, said control means processes said interrupt request supplied to said first receiving means, on a basis of a result of the large-and-small relation comparison by said comparison means and a content of said flag indicating a predetermined status of an interrupt request.