Patent US5348901A successfully refreshed from Google Patents.
US5348901A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interconnect and resistor for integrated circuits
Assignee: STMicroelectronics lnc USA
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Filing: 1992-07-09
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Granted: 1994-09-20
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Expires: 2012-07-09
Abstract
Abstract A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.
Inventors
- 👤 Fusen E. Chen
- 👤 Girish A. Dixit
- 👤 Robert O. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:25
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
146 words
A method for forming a polycrystalline silicon resistive load element in a semiconductor integrated circuit, comprising the steps of: forming a first conductive layer wherein the first conductive layer has a first region of a first conductivity type and a second region of a second conductivity type wherein a junction is formed between the first and the second regions; forming a first oxide region over the second region of the first conductive layer and the junction; depositing an undoped oxide layer over the integrated circuit; performing an etchback of the undoped oxide layer to form sidewall oxide spacers on the sidewalls of the first oxide region covering the junction and a portion of the first region of the first conductive layer adjacent to the junction; and forming a silicide region over the first region of the first conductive layer not covered by the sidewall oxide spacer.
Claim 2
Independent Claim
146 words
A method for forming a polycrystalline silicon resistive load element in a semiconductor integrated circuit, comprising the steps of: forming a first conductive layer wherein the first conductive layer has a first region of a first conductivity type and a second region of a second conductivity type wherein a junction is formed between the first and the second regions; forming a first oxide region over the second region of the first conductive layer and the junction; depositing an undoped oxide layer over the integrated circuit; performing an etchback of the undoped oxide layer to form sidewall oxide spacers on the sidewalls of the first oxide region covering the junction and a portion of the first region of the first conductive layer adjacent to the junction; and forming a silicide region over the first region of the first conductive layer not covered by the sidewall oxide spacer.
Claim 3
Dependent Claim
14 words
The method of claim 1, wherein the first conductive layer is a polysilicon layer.
Claim 4
Dependent Claim
14 words
The method of claim 1, wherein the first conductive layer is a polycide layer.
Claim 5
Dependent Claim
18 words
The method of claim 1, wherein the first conductive layer's first region is implanted with a N-type dopant.
Claim 6
Dependent Claim
11 words
The method of claim 4, wherein the N-type dopant is arsenic.
Claim 7
Dependent Claim
18 words
The method of claim 1, wherein the first conductive layer's second region is implanted with a P-type dopant.
Claim 8
Dependent Claim
11 words
The method of claim 6, wherein the P-type dopant is boron.
Claim 9
Dependent Claim
18 words
The method of claim 1, wherein the first conductive layer has a thickness of between approximately 500-2000 angstroms.
Claim 10
Dependent Claim
36 words
The method of claim 1, wherein a second oxide region is disposed under the first conductive layer and wherein the second oxide region has an opening therethrough exposing a portion of an underlying second conductive layer.
Claim 11
Dependent Claim
22 words
The method of claim 9, wherein the first conductive layer is further disposed over the exposed portion of the second conductive layer.
Claim 12
Dependent Claim
41 words
The method of claim 1, wherein the silicide forming step further comprises the steps of: forming a metal silicide forming layer over the integrated circuit; annealing the metal silicide forming layer; and, removing unreacted metal from the metal silicide forming layer.
Claim 13
Dependent Claim
21 words
The method of claim 11, wherein the metal silicide forming layer is deposited to a depth of between approximately 200-1000 angstroms.
Claim 14
Dependent Claim
15 words
The method of claim 12, wherein the metal silicide forming layer is a refractory metal.
Claim 15
Dependent Claim
11 words
The method of claim 13, wherein the refractory metal is titanium.
Claim 16
Independent Claim
139 words
A method of forming a polycrystalline silicon resistive load element in a semiconductor integrated circuit, comprising the steps of: forming a lightly doped first conductive layer having a conductivity of a first type; forming a first oxide layer over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer; using the first oxide layer as a mask, implanting the exposed portion of the first conductive layer with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask; depositing an undoped oxide layer over the integrated circuit; performing an etchback of the undoped oxide layer to form a sidewall oxide spacer of the sidewall of the first oxide layer; and forming a silicide over the exposed portion of the first conductive layer.
Claim 17
Independent Claim
139 words
A method of forming a polycrystalline silicon resistive load element in a semiconductor integrated circuit, comprising the steps of: forming a lightly doped first conductive layer having a conductivity of a first type; forming a first oxide layer over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer; using the first oxide layer as a mask, implanting the exposed portion of the first conductive layer with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask; depositing an undoped oxide layer over the integrated circuit; performing an etchback of the undoped oxide layer to form a sidewall oxide spacer of the sidewall of the first oxide layer; and forming a silicide over the exposed portion of the first conductive layer.
Claim 18
Dependent Claim
20 words
The method of claim 15, wherein the first conductive layer is disposed over a portion of a second conductive layer.
Claim 19
Dependent Claim
14 words
The method of claim 15, wherein the first conductive layer is a polysilicon layer.
Claim 20
Dependent Claim
14 words
The method of claim 15, wherein the first conductive layer is a polycide layer.
Claim 21
Dependent Claim
12 words
The method of claim 15, wherein the first conductivity type is P-type.
Claim 22
Dependent Claim
12 words
The method of claim 15, wherein the second conductivity type is N-type.
Claim 23
Dependent Claim
20 words
The method of claim 15, wherein the first conductive layer has a thickness of between approximately 500 to 2000 angstroms.
Claim 24
Dependent Claim
24 words
The method of claim 15, wherein the first oxide layer and second oxide region have a thickness of between approximately 900 to 2000 angstroms.
Claim 25
Dependent Claim
42 words
The method of claim 15, wherein the silicide forming step further comprises the steps of: forming a metal silicide forming layer over the integrated circuit; annealing the metal silicide forming layer; and, removing any unreacted metal from the metal silicide forming layer.
Claim 26
Dependent Claim
21 words
The method of claim 23, wherein the metal silicide forming layer is deposited to a depth of between approximately 200-1000 angstroms.
Claim 27
Dependent Claim
15 words
The method of claim 24, wherein the metal silicide forming layer is a refractory metal.
Claim 28
Dependent Claim
11 words
The method of claim 25, wherein the refractory metal is titanium.
Claim 29
Independent Claim
142 words
A method of forming a polycrystalline silicon resistive load element in a semiconductor integrated circuit, comprising the steps of: forming a first conductive layer wherein the first conductive layer has a first region of a first conductivity type and a second region of a second conductivity type wherein a junction is formed between the first and the second regions; forming a first oxide region over the first region of the first conductive layer and the junction; depositing an undoped oxide layer over the integrated circuit; patterning and etching the undoped oxide layer to form an undoped oxide region over the first oxide region, the junction and a portion of the first region of the first conductive layer adjacent to the junction; and forming a silicide region over the second region of the first conductive layer not covered by the undoped oxide layer.
Claim 30
Independent Claim
142 words
A method of forming a polycrystalline silicon resistive load element in a semiconductor integrated circuit, comprising the steps of: forming a first conductive layer wherein the first conductive layer has a first region of a first conductivity type and a second region of a second conductivity type wherein a junction is formed between the first and the second regions; forming a first oxide region over the first region of the first conductive layer and the junction; depositing an undoped oxide layer over the integrated circuit; patterning and etching the undoped oxide layer to form an undoped oxide region over the first oxide region, the junction and a portion of the first region of the first conductive layer adjacent to the junction; and forming a silicide region over the second region of the first conductive layer not covered by the undoped oxide layer.
Claim 31
Independent Claim
135 words
A method of forming a polycrystalline silicon resistive load element in a semiconductor integrated circuit, comprising the steps of: forming a lightly doped first conductive layer having a conductivity of a first type; forming a first oxide layer over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer; using the first oxide layer as a mask, implanting the exposed portion of the first conductive layer with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask; depositing an undoped oxide layer over the integrated circuit; patterning and etching the undoped oxide layer to again expose an implanted portion of the first conductive layer; and forming a silicide over the exposed portion of the first conductive layer.
Claim 32
Independent Claim
135 words
A method of forming a polycrystalline silicon resistive load element in a semiconductor integrated circuit, comprising the steps of: forming a lightly doped first conductive layer having a conductivity of a first type; forming a first oxide layer over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer; using the first oxide layer as a mask, implanting the exposed portion of the first conductive layer with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask; depositing an undoped oxide layer over the integrated circuit; patterning and etching the undoped oxide layer to again expose an implanted portion of the first conductive layer; and forming a silicide over the exposed portion of the first conductive layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-19 | 1998-03-21 | 1998-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-19 | 2002-03-21 | 2002-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-19 | 2006-03-21 | 2006-09-20 | $7700.00 | Window Closed / Lapsed |