US5107322A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wiring or conductor interconnect for a semiconductor device or the like
Assignee: Seiko Epson Corp
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Filing: 1989-09-22
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Granted: 1992-04-21
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Expires: 2009-09-22
Abstract
Abstract A wiring or conductor structure for an integrated circuit structure of a semiconductor device is designed to provide for extended values in integrated passive components, for example, resistance values in a memory cell of a high resistance load type static RAM. Extended values of high resistance polycrystalline silicon resistances formed in conductor films are achieved by effectively increasing the length of the films and, therefore, the regions of resistance without changing or increasing the size or scale of the semiconductor device. This is accomplished by employing double wiring or conductor layers which are electrically connected permitting a lateral extension of the integrated and patterned resistance region in at least one of the wiring layers while retaining or further reducing the integration scale of the active and passive components comprising the integrated circuit structure.
Inventors
- 👤 Masakazu Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:50
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10B10/15
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
282 words
In an integrated circuit, interconnect means to extend the value of an integrated passive electrical component coupled to other passive and active electrical elements in said circuit, at least some of said active electrical elements including diffusion regions, said extended value provided without any change in or allowing for a reduction in the scale of integration among said electrical elements, said interconnect means comprising at least two conductor layers separated by an insulating layer with a second of said conductive layers comprising said integrated passive electrical component formed therein for a substantial length thereof, a first of said conductor layers connected at one end through a first contact hole to a diffusion region of at least one of said active electrical elements and laterally extended relative to said one electrical element in a first direction to a permissible extremity wherein the other end of said first conductor layer is electrically coupled to one end of said second conductive layer through said insulating layer via a second contact hole offset from said first contact hole providing a tiered formation of first and second conductor layers coupled at said extremity, said first conductor layer providing electrical connection between said one active element and said second layer and said second layer and said integrated passive electrical component having an extended conductor length extending laterally away from said second contact hole in a second direction opposite to said first direction over and insulated from said first contact hole, said integrated passive electrical component in said second conductor layer formed in spaced relation from said second contact hole with the magnitude of said integrated passive electrical component extended due to the addition of said extended conductor length.
Claim 2
Dependent Claim
282 words
In an integrated circuit, interconnect means to extend the value of an integrated passive electrical component coupled to other passive and active electrical elements in said circuit, at least some of said active electrical elements including diffusion regions, said extended value provided without any change in or allowing for a reduction in the scale of integration among said electrical elements, said interconnect means comprising at least two conductor layers separated by an insulating layer with a second of said conductive layers comprising said integrated passive electrical component formed therein for a substantial length thereof, a first of said conductor layers connected at one end through a first contact hole to a diffusion region of at least one of said active electrical elements and laterally extended relative to said one electrical element in a first direction to a permissible extremity wherein the other end of said first conductor layer is electrically coupled to one end of said second conductive layer through said insulating layer via a second contact hole offset from said first contact hole providing a tiered formation of first and second conductor layers coupled at said extremity, said first conductor layer providing electrical connection between said one active element and said second layer and said second layer and said integrated passive electrical component having an extended conductor length extending laterally away from said second contact hole in a second direction opposite to said first direction over and insulated from said first contact hole, said integrated passive electrical component in said second conductor layer formed in spaced relation from said second contact hole with the magnitude of said integrated passive electrical component extended due to the addition of said extended conductor length.
Claim 3
Dependent Claim
47 words
In the integrated circuit of claim 1 wherein said circuit comprises a memory cell in a high resistance load type static RAM, said passive electrical component comprising a resistance wherein the resistance value thereof is increased due to said extended conductor length in said second conductor layer.
Claim 4
Dependent Claim
241 words
In a semiconductor device having a memory cell including a transistor formed on a semiconductor substrate and a high resistance load, said semiconductor device comprising a first insulating film formed over said transistor, a first contact hole formed in said first insulating film aligned with an electrode domain of said semiconductor device containing doping impurities, a first wiring layer formed on said first insulating film and connected to said electrode domain through said first contact hole and extended laterally over said first insulating film in a first direction to an extended position, a second insulating film formed on said first wiring layer, a second contact hole formed in said second insulating film aligned with said extended position and thereby laterally offset relative to said first contact hole in said first direction, a second wiring layer comprising an integral resistance region for a substantial length thereof, said second wiring layer formed on said second insulating film and coupled at said extended position to said laterally extended first wiring layer, said second wiring layer and said integral resistance region extending over said second insulating film and said first contact hole in a second direction opposite to said first direction, said integral resistance region formed in said second wiring layer in spaced relation from said second contact hole thereby protected from the possible migration of said impurities from said electrode domain via said first wiring layer into the region of said second contact hole.
Claim 5
Dependent Claim
241 words
In a semiconductor device having a memory cell including a transistor formed on a semiconductor substrate and a high resistance load, said semiconductor device comprising a first insulating film formed over said transistor, a first contact hole formed in said first insulating film aligned with an electrode domain of said semiconductor device containing doping impurities, a first wiring layer formed on said first insulating film and connected to said electrode domain through said first contact hole and extended laterally over said first insulating film in a first direction to an extended position, a second insulating film formed on said first wiring layer, a second contact hole formed in said second insulating film aligned with said extended position and thereby laterally offset relative to said first contact hole in said first direction, a second wiring layer comprising an integral resistance region for a substantial length thereof, said second wiring layer formed on said second insulating film and coupled at said extended position to said laterally extended first wiring layer, said second wiring layer and said integral resistance region extending over said second insulating film and said first contact hole in a second direction opposite to said first direction, said integral resistance region formed in said second wiring layer in spaced relation from said second contact hole thereby protected from the possible migration of said impurities from said electrode domain via said first wiring layer into the region of said second contact hole.
Claim 6
Dependent Claim
33 words
In the semiconductor device as defined in claim 3 wherein said second wiring layer is extended laterally in said second direction away from said second contact hole and constituting said high resistance load.
Claim 7
Dependent Claim
32 words
In the semiconductor device as defined in claim 3 wherein said first wiring layer is connected to said electrode domain via a combination layer comprising a polysilicon film and a silicide film.
Claim 8
Dependent Claim
19 words
In the semiconductor device as defined in claim 3 wherein said second wiring layer comprises a polycrystalline silicon layer.
Claim 9
Dependent Claim
19 words
In the semiconductor device as defined in claim 3 wherein said second wiring layer resistor means comprises intrinsic silicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-21 | 1995-10-21 | 1996-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-21 | 1999-10-21 | 2000-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-21 | 2003-10-21 | 2004-04-21 | $7700.00 | Window Closed / Lapsed |