Latid implants for increasing the effective width of transistor elements in a semiconductor device

Claim 1

A method for increasing the effective width of a P-type channel connecting N-type source and drain regions of a transistor element further comprising a gate which transistor element is located on the surface of a P-type substrate and is separated from other transistor elements on the substrate by field oxide and P-type channel-stop implants which method comprises the steps of: (a) tilting a transistor-free substrate having P-type field stop implants and field oxide regions which substrate contains a silicon nitride layer over all portions of the substrate surface except over the field oxide regions wherein said substrate is tilted at an angle of from greater than 0° to less than 90° relative to the direction of an N-type ion beam; (b) ion-implanting N-type ion dopant into the tilted substrate; (c) rotating the substrate while retaining or later reestablishing the tilt and repeating step (b) until all of the substrate has been exposed to ion-implantation; (d) thermally treating the substrate produced in step (c) above so as to activate the dopants; and (e) completing fabrication of said transistor element on the surface of said substrate wherein sufficient N-type dopant is implanted into the substrate so that the threshold voltage in the boundary of the P-type channel of said transistor element is reduced.

Claim 2

A method for increasing the effective width of a P-type channel connecting N-type source and drain regions of a transistor element further comprising a gate which transistor element is located on the surface of a P-type substrate and is separated from other transistor elements on the substrate by field oxide and P-type channel-stop implants which method comprises the steps of: (a) tilting a transistor-free substrate having P-type field stop implants and field oxide regions which substrate contains a silicon nitride layer over all portions of the substrate surface except over the field oxide regions wherein said substrate is tilted at an angle of from greater than 0° to less than 90° relative to the direction of an N-type ion beam; (b) ion-implanting N-type ion dopant into the tilted substrate; (c) rotating the substrate while retaining or later reestablishing the tilt and repeating step (b) until all of the substrate has been exposed to ion-implantation; (d) thermally treating the substrate produced in step (c) above so as to activate the dopants; and (e) completing fabrication of said transistor element on the surface of said substrate wherein sufficient N-type dopant is implanted into the substrate so that the threshold voltage in the boundary of the P-type channel of said transistor element is reduced.