Method and circuitry for screening a dynamic memory device for defective circuits

Claim 2

A dynamic memory device with power and ground terminals and having a row address buffer and a column address buffer, the device comprising: a refresh counter connected to the row and column address buffers; a row circuit connected to the row address buffer; a column circuit connected to the column address buffer; and control circuitry receiving a screening signal and controlling the dynamic memory device to operate in a designated mode according to the screening signal, the designated mode including one of a normal mode and a screening refresh mode, the normal mode including one of a CBR (CAS Before ROR) mode and an ROR (RAS Only Refresh) mode, the screening refresh mode applying a dynamic stress uniformly to and exposing latent defects in the dynamic memory device, the control circuitry combining the screening signal with at least one of an RAS(Row Address Strobe) and a CAS (Column Address Strobe) to designate the screening refresh mode, the control circuitry activating the refresh counter, the row circuit and the column circuit when the screening refresh mode is designated and power is applied between the power and ground terminals at a supply voltage greater than a normal working voltage.

Claim 3

The dynamic memory device according to claim 1, wherein said row circuit includes a row decoder, a memory cell array, and a sense amplifier, and said column circuit includes a column decoder and an I/O (Input/Output) gate.

Claim 4

The dynamic memory device according to claim 1, further comprising a CAS terminal for receiving the CAS and an RAS terminal for receiving the RAS and an additional terminal, wherein said screening refresh mode is set using only the power terminal, the ground terminal, the RAS terminal, the CAS terminal, and the additional terminal.

Claim 5

The dynamic memory device according to claim 1, further comprising a CAS terminal for receiving the CAS and an RAS terminal for receiving the RAS and a WE terminal and an additional terminal, wherein said screening refresh mode is set using only the power terminal, the ground terminal, the RAS terminal, the CAS terminal, the WE terminal, and the additional terminal.

Claim 6

The dynamic memory device according to claim 1, further comprising an RAS terminal for receiving the RAS and an additional terminal, wherein said screening refresh mode is set using only the power terminal, the ground terminal, the RAS terminal, and the additional terminal.

Claim 7

The dynamic memory device of claim 1, wherein the refresh counter outputs a refresh address signal, the refresh address signal being supplied to both the row address buffer and the column address buffer.

Claim 8

The dynamic memory device of claim 1, wherein the refresh counter includes a row refresh counter and a column refresh counter, the row refresh counter outputting a row refresh address signal supplied to the row address buffer, the column refresh counter outputting a column address signal supplied to the column address buffer.

Claim 9

The dynamic memory device of claim 1, further comprising a dedicated screening terminal for receiving signal external to the dynamic memory device, the screening signal being input from the dedicated screening terminal.

Claim 10

The dynamic memory device of claim 1, wherein the control circuitry designates the screening refresh mode when a WE (write enable) signal, an address key code and the CAS is received by the control circuitry before the RAS while the control circuitry is receiving the screening signal.

Claim 11

The dynamic memory device of claim 1, wherein the control circuitry includes: detecting circuitry for detecting an order in which signals received by the control circuitry are received; designating circuitry for designating the designated mode as being the normal mode when the detected order of the signals received by the control circuitry is a first order, and for designating the designated mode as being the screening refresh mode when the detected order of the signals received by the control circuitry is a second order, different from the first order.

Claim 12

The dynamic memory device of claim 1, further comprising an arbitrary terminal, wherein: an arbitrary signal received at the arbitrary terminal by the control circuitry is characterized as having a potential within a normal potential range when the control circuitry controls the dynamic memory device to operate in the normal mode; and the control circuitry includes (1) detection circuitry for detecting when the arbitrary signal is received by the control circuitry while being characterized as having a potential outside of the normal potential range, and (ii) designating circuitry for designating the designated mode as being the screening refresh mode when the detection circuitry detects the arbitrary signal as being received by the control circuitry while being characterized as having a potential outside of the normal potential range.

Claim 13

The dynamic memory device of claim 1, wherein the control circuitry controls the dynamic memory device to operate in the screening refresh mode while the dynamic memory device is unseparated from a wafer having a plurality of circuits.

Claim 14

A dynamic memory device which inputs an RAS (Row Address Strobe) and a CAS (Column Address Strobe) to designate one of a CBR (CAS Before RAS) mode and an ROR (RAS Only Refresh) mode, each of the CBR and ROR modes constituting a normal operating mode, the dynamic memory device comprising: a clock generator; a refresh counter incremented by the clock generator for generating an output signal; a row address buffer for receiving one of a row address signal and a first part of the output signal of said refresh counter; a row circuit connected to the row address buffer; a column address buffer for receiving one of a column address signal and a second part of the output signal of said refresh counter; a column circuit connected to the column address buffer and the row circuit; and a screening refresh mode setting circuit, receiving a screening signal, for (i) outputting a detection signal when the screening signal is received while the RAS and CAS are designating one of the CBR and ROR modes, (ii) designating a screening refresh mode when the screening refresh mode setting circuit outputs the detection signal, (iii) activating the clock generator, refresh counter, row address buffer, row circuit, column address buffer and column circuit when the screening mode refresh setting circuit outputs the detection signal and (iv) designating one of the normal operating modes when the screening refresh mode setting circuit does not output the detection signal.

Claim 15

A dynamic memory device which inputs an RAS (Row Address Strobe) and a CAS (Column Address Strobe) to designate one of a CBR (CAS Before RAS) mode and an ROR (RAS Only Refresh) mode, each of the CBR and ROR modes constituting a normal operating mode, the dynamic memory device comprising: a clock generator; a refresh counter incremented by the clock generator for generating an output signal; a row address buffer for receiving one of a row address signal and a first part of the output signal of said refresh counter; a row circuit connected to the row address buffer; a column address buffer for receiving one of a column address signal and a second part of the output signal of said refresh counter; a column circuit connected to the column address buffer and the row circuit; and a screening refresh mode setting circuit, receiving a screening signal, for (i) outputting a detection signal when the screening signal is received while the RAS and CAS are designating one of the CBR and ROR modes, (ii) designating a screening refresh mode when the screening refresh mode setting circuit outputs the detection signal, (iii) activating the clock generator, refresh counter, row address buffer, row circuit, column address buffer and column circuit when the screening mode refresh setting circuit outputs the detection signal and (iv) designating one of the normal operating modes when the screening refresh mode setting circuit does not output the detection signal.

Claim 16

In a dynamic memory circuit with power and ground terminals, a screening signal input terminal, and at least one input mode terminal for receiving at least one corresponding signal, the at least one corresponding signal being for designating a normal refresh mode, the normal refresh mode being one of an ROR (RAS Only Refresh) mode and a CBR (CAS Before RAS) mode, a method for stress testing the dynamic memory circuit comprising steps of: applying power between the power and ground terminals at a supply voltage greater than a normal working voltage for the dynamic memory device; supplying the screening signal to the screening signal input terminal from an external screening signal source; and designating a designated mode, the designated mode being one of the CBR mode and the ROR mode so that the dynamic memory device operates in a screening refresh mode when the screening signal is supplied to the dynamic memory device.

Claim 17

In a dynamic memory circuit with power and ground terminals, a screening signal input terminal, and at least one input mode terminal for receiving at least one corresponding signal, the at least one corresponding signal being for designating a normal refresh mode, the normal refresh mode being one of an ROR (RAS Only Refresh) mode and a CBR (CAS Before RAS) mode, a method for stress testing the dynamic memory circuit comprising steps of: applying power between the power and ground terminals at a supply voltage greater than a normal working voltage for the dynamic memory device; supplying the screening signal to the screening signal input terminal from an external screening signal source; and designating a designated mode, the designated mode being one of the CBR mode and the ROR mode so that the dynamic memory device operates in a screening refresh mode when the screening signal is supplied to the dynamic memory device.

Claim 18

The method of claim 14, wherein the step of supplying includes supplying the screening signal while the dynamic memory device is unseparated from a wafer having a plurality of circuits.

Claim 19

The method of claim 14, further comprising a step of generating a column address and connecting the column address to a column circuit of the dynamic memory device when the designated mode is designated while the screening signal is supplied.

Claim 20

The method of claim 16, wherein the step of generating includes uniformly applying a voltage stress to the column circuit.

Claim 21

The method of claim 14, further comprising a step of generating a data signal and a read/write signal and connecting the data and read/write signals to a column circuit of the dynamic memory device when the designated mode is designated while the screening signal is supplied, the row circuit including a memory cell array with at least one transfer gate.

Claim 22

The method of claim 18, wherein the step of generating includes uniformly applying a voltage stress to a first transfer gate of the memory cell array.

Claim 23

The method of claim 14, further comprising a step of operating a data output buffer of the dynamic memory device when the designated mode is designated while the screening signal is supplied.

Claim 24

The method of claim 20, wherein the step of operating includes uniformly applying a voltage stress to the data output buffer.